Abstract: The present invention relates to a system (1) comprising a controllable device (10) for executing a program; and a carrier (30) having a surface comprising a plurality of surface markings (34, 36), each marking being located over a RF tag embedded in the carrier, each RF tag comprising a unique identification code, wherein the program, when executed on the controllable device, is adapted to generate a plurality of selectable options, each of said options being selectable by one of the unique identification codes. In an embodiment, the system further comprises an RF reader (20) for communicating said identification codes to the controllable device (10), wherein the controllable device (10) is arranged to interpret each identification code as an input signal for said program. Such a system may be controlled by means of the carrier (30), thus obviating the need for button-based remote controllers. This is particularly useful in gaming applications.
Type:
Application
Filed:
July 31, 2009
Publication date:
September 29, 2011
Applicant:
NXP B.V.
Inventors:
David Tarrant, Ian Waldock, Alister Lam, Alan Glynne-Jones, Nick David Lane Thorne
Abstract: The invention relates to multi-channel audio signal processing, in particular to a method of processing a multi-channel audio signal and to a signal processing device.
Type:
Application
Filed:
March 24, 2011
Publication date:
September 29, 2011
Applicant:
NXP B.V.
Inventors:
Erik Gosuinus Petrus SCHUIJERS, Sebastiaan de Bont
Abstract: A device (100) for modelling a physical structure by a number of finite state machines comprising a simulation unit (114) adapted for simulating the physical structure by a number of finite state machines, a recording unit (104) adapted for recording state transitions for the number of finite state machines during simulating the physical structure on the basis of the number of finite state machines, and an analysis unit (106) adapted for analysing the recorded state transitions after simulating the physical structure on the basis of the number of finite state machines.
Abstract: The present application relates to a method for driving a sigma delta modulator. The present application relates also to a sigma delta modulator comprising at least one integrator device and one quantizer device and it relates to a readable medium having a computer program stored thereon for performing said method. The method comprises setting a sigma delta modulator to an irrational operation mode. The method comprises monitoring at least one output signal of the sigma delta modulator. The method comprises resetting the sigma delta modulator to the irrational operation mode depending on the monitored output signal.
Abstract: A method of manufacturing a resistive divider circuit, includes providing a silicon body having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem supporting a relatively wider silicon platform. A silicidation protection (SIPROT) layer is deposited over the body and intermediate taps and then patterned to expose the platform. A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.
Abstract: A data communication system, comprising at least three signal conductors and a first and a second power supply terminal, for supplying currents of mutually opposite direction to the signal conductors respectively. A driver circuit establishes respective combinations of currents through the signal conductors from a selectable set of combinations, which includes combinations with currents from the first supply terminal and to the second supply terminal, so that a sum of the currents through the signal conductors substantially has a same value for each combination and at least one of the conductors in operation does not merely function in a differential-pair relation with another one of the conductors, the driver circuit determining which of the combinations from the set are established depending on information to be transmitted.
Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).
Type:
Grant
Filed:
August 29, 2007
Date of Patent:
September 27, 2011
Assignee:
NXP B.V.
Inventors:
Johannes J. T. M. Donkers, Sebastien Nuttinck, Guillaume L. R. Boccardi, Francois Neuilly
Abstract: A method for obtaining tickets for journeys in a passenger transportation system (VSY) which comprises stations (S11 . . . S00) for entering and/or leaving transport means (VM1, VM2) of the system (VSY) for journeys between the stations (S11 . . . S00), wherein at least one station (S11 . . . S00) of the system (VSY) is assigned at least one contactlessly readable data carrier (T11 . . . T00) and/or at least one transport means (VM 1, VM2) of the system (VSY) is assigned at least one contactlessly readable data carrier (T10, T20), wherein the contactlessly readable data carriers (T11 . . . T00; T10, T20) contain ticket information items (IN11, IN23, INOO), and one of the contactlessly readable data carriers (T11 . . . T00; T10, T20) is read by a mobile reader (MOD) in at least one station (S11 . . . S00) and/or in at least one transport means (VM1, VM2), and the corresponding ticket information item or items (IN11, IN23, IN00) is/are stored in the mobile reader (MOD).
Abstract: A method of operating battery power management unit (PMU) in over-discharge situation is disclosed. Furthermore, a power management unit (PMU) and a device comprising a power management unit (PMU) are disclosed. The power management unit (PMU) is part of a system, comprising a battery and a safety circuit connected to the battery. The state of the safety circuit of the battery is determined and the on/off control of the device is made inactive while the safety circuit remains active. Thereby avoiding an application run on the device to go into an active state, i.e. to be turned on, at a moment when the battery has not returned to its normal operation mode.
Type:
Grant
Filed:
May 1, 2006
Date of Patent:
September 27, 2011
Assignee:
NXP B.V.
Inventors:
Lambertus Franciscus Maria De Koning, Eddy Aziz
Abstract: The invention relates to normalisation of a TDC system (20). The TDC system (20) comprises a TDC core (21), a gain normalization circuit (22) and an adjuster (23). The TDC core (21) comprises a set of nominally identical delay elements and converts the time difference between the edges of a reference clock signal (FREF) and a controllable clock signal (CLK) into a raw TDC output code as a digital word. The adjuster (23) is configured to carry out the gain normalisation by adjusting the output code. The gain normalization circuit (22) comprises at least a processor for analyzing the occurrence probability of the output code values, and for determining the adjustment to be made by the adjuster (23) according to said occurrence probability.
Abstract: A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory.
Abstract: A circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor. The processor configured to process such power control instructions and to maintain the power modes of the multiple hardware resources to that specified in an earlier-processed power control instruction, such that subsequently-processed instructions will be processed while the power modes of the multiple hardware resources are set to that specified by the earlier-processed power control instruction.
Abstract: The invention concern a display device comprising a liquid crystal material between a first substrate provided with row electrodes (7) and a second substrate provided with column electrodes (6), in which overlapping parts of the row and column electrodes define pixels (8), driving means (5) for driving the column electrodes (6) in conformity with an image to be displayed, and driving means (4) for driving the row electrodes (7), wherein the row electrodes (7) select at least one row during a row selection time and column voltages (Gj(t)) are supplied to the column electrodes (6), wherein the column voltage waveform depends on the grey scale to be displayed by the driven pixel in a certain column and depends on a used selection signal (Fi) for the selected row, wherein a column voltage (Gj(t)) is switchable between at least two different column voltage levels during a row selection time.
Abstract: A current-steered DAC has first and second differential outputs for providing an analog output signal under control of a digital input signal. In operational use of the DAC, the output signal has a differential component, which is representative of the digital input signal, and also has a first common-mode component. The DAC has circuitry operative to add an extra common-mode component to both the first and second differential outputs so as to make a sum of the first common-mode component and the extra common-mode component substantially independent of a state change of the digital input signal.
Abstract: A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.
Abstract: In order to further develop a circuit arrangement for as well as a method of performing an inversion operation in a cryptographic calculation, wherein only inversion modulo an odd number is allowed, it is proposed that the inversion operation is performed modulo at least one even number.
Abstract: A wireless terminal is described, which is formed from a module (20) comprising a substrate, RF components (32, 33), an antenna (25), notably of the PIFA type, and a linkage part (30) for linking the antenna to the substrate. The RF components are placed in the vicinity of the linkage part or even on the linkage part without degrading the operation of the antenna. By placing the RF components on this link, an area is made available for circuitry on the substrate.
Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.
Abstract: In a method of inventorizing a plurality of data carriers (2) with the aid of a communication station (1) communicating in a contact-free way with the data carriers (2), a set (TS(1), TS(2), . . . TS(N), TS(N+1), . . . (TS(K)) of transmission parameters, preferably of time slots (TS) is available, which set comprises a first subset (TS(1) . . . TS(N)) and a second subset (TS(N+1) . . . (TS(K)) wherein inventorizing procedures (MP1, MP2, MP3, . . . ) are performed consecutively and wherein uninventorized data carriers (2) transmit their identification data (ID) to the communication station (1) for the purpose of inventorization only using transmission parameters contained in the first subset and wherein already inventorized data carriers (2) transmit their identification data (ID) to the communication station (1) only using transmission parameters contained in the second subset.
Abstract: A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.
Type:
Grant
Filed:
December 31, 2009
Date of Patent:
September 20, 2011
Assignee:
NXP B.V.
Inventors:
Marcel J. M. Pelgrom, Hendricus J. M. Veendrick, Victor Zieren