Abstract: A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N; IM). The memory controller (SMC) comprises a first interface (PI) for connecting the memory controller (SMC) to the network (N; IM). The first interface (PI) is arranged for receiving and transmitting data streams (ST1-ST4). A streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N; IM) and the memory (MEM). Said streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4). A buffer managing unit (BMU) is provided for managing a temporarily storing of data streams (ST1-ST4) in the buffer (B) in a first and second operation mode (1OM; 2OM). In the first operation mode (1OM), data from the data streams (ST1-ST4) to be stored in the memory (MEM) are temporarily stored in the buffer (B) until a portion of the buffer (B) is occupied.

Abstract: An RFID system comprises at least one reading device (1) and at least one transponder (2, 2?, 2?, 2??), which are configured for non-contact communication by means of modulated electromagnetic signals (SS), which contain data and/or commands packed in data frames, in which the reading device (1) is configured for transmitting a group of data frames (D-SYNC), which contain synchronization information (Preamble, Start Delimiter) for synchronization with the transponder (2, 2?, 2?, 2??) and to transmit another group of data frames (D-NOSYNC) which do not contain such synchronization information, in which the transponder (2, 2?, 2?, 2??) has synchronization means (14, 20, 21) which are configured to effect synchronization with the reading device (1) with the help of synchronization information (Preamble, Start Delimiter) contained in received data frames (D-SYNC) and synchronization status test means (15,15?,15?,22) configured for detecting whether the transponder runs synchronously with the reading device and in

Abstract: A sampling circuit includes multiple sampling channels adapted to sample the signal in time-multiplexed fashion. Each sampling channel includes a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. In an embodiment, the holding time period includes a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.

Abstract: The present invention relates to a low-voltage self-calibrated peak detector (100). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (122, 128, 130), the peak detection is made accurate whatever temperature, process or mismatch spreads. Its input bandwidth can be as high as the bandwidth of an operational amplifier of unity gain. In a rail-to-rail configuration, it can be implemented into a fully differential low-voltage self-calibrated CMOS peak detector (200), which can have a very high conversion gain (?) and a very high input signal dynamic ranging.

Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semi-conductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: Apparatus and method for IR-drop and supply noise measurements electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.

Abstract: A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer.

Abstract: The invention describes a charge-pump circuit (1, 1?) comprising a supply voltage input node (10) for applying an input voltage (Uin) to be boosted, a boosted voltage output node (11) for outputting a boosted voltage (Uout), and a plurality of transistor stages connected in series between the supply voltage input node (10) and the boosted voltage output node (11), wherein at least one transistor stage comprises a multiple-gate transistor (D1, . . . , D5), which transistor (D1, . . . , D5) comprises at least two gates, of which one is a first gate (G) for switching the transistor (D1, . . . , D5) on or off according to a voltage applied to the first gate (G), and one is an additional second gate (Gi) for controlling the threshold voltage of the multiple-gate transistor (D1, . . . , D5), independently of the first gate (G), according to a control voltage (?1, ?2) applied to the second gate (Gi).

Abstract: In an example embodiment, a system detects the degree of rotation of a knob, the system comprises a shaft having a length and a first end and a second end; the second end has an oblique reflective surface defined thereon; the first end fixedly attached to the knob. Containing the shaft is a rotation body, having a receptacle to accommodate the second end of the shaft with the oblique reflective surface exposed. An integrated circuit optical module is optically coupled the rotation body and the optical module detects light irradiance profile from the oblique reflective surface. The optical module includes a solid state light source and a plurality of photo detectors which generate an electrical signal upon exposure to light. As the knob is rotated, the oblique reflective surface generates a changing asymmetric irradiance profile, the change being translated into an electrical signal via the photo detectors. The electrical signal corresponds to the degree of rotation of the knob.

Abstract: The present invention relates in general to the field of integrated circuits, and more specifically to a meander resistor. Basically, a meander resistor can be considered as a bar resistor with the exception of the corner squares (right-angle bends). The Electrostatic Discharge (ESD) sensitivities of on-chip resistors can be a problem for both electronic manufactures and electronic component users. As others components, passive devices are known to be susceptible to ESD events. The context of this invention is to improve the reliability of the resistors during an ESD event. An ESD stress means that high current and high voltage levels are applied to the device. The device has to be able to dissipate this energy without failure.

Abstract: A portable mobile communication device (10) has a mobile host processor (104) permanently installed in the portable mobile communication device (10) and a near field communication circuit (100) comprising a non-volatile memory (101). Configuration data is maintained in the non-volatile memory (101) of the near field communication circuit (100), for control of communication dependent on the configuration data. Prior to communication between the near field communication circuit (100) and the mobile host processor (104) a session identity value is tested. If the session identity value does not match a reference value, at least part of the configuration data for the communication channel is initialized, after which the session identity value and the reference value are equalized after setting up the configuration data. If the session identity value matches the reference value, the mobile host processor (104) proceeds with communication without said initialization.

Abstract: This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit.

Abstract: A method of controlling a Fluorescent Lamp (CFL) is disclosed, which enables the lamp to be dimmed during a quick-start mode in which the lamp current may be boosted. The method involves determining a boost value and a dimming value, and controlling the lamp power in dependence on the boost and dimming values. A dimming threshold may be set, below which (i.e. at dimmer output light levels) the boost function is disabled. Hysteresis may be included in the control, in order to avoid hopping between modes. A controller for use with a fluorescent lamp which is adapted to operate according to such a method and a fluorescent lamp using such a controller are also disclosed.

Abstract: The present invention describes a gaming system comprising a near-field communication device (30) and a plurality of transmission tags (10), wherein the near-field communication device is arranged to adapt the content stored in a transmission tag upon establishing a communicative connection with the transmission tag. This for instance facilitates the programming of game parameters in e.g. a treasure hunt game or an adventure game into the transmission tags either before or during play.

Abstract: A contactless tag reader device comprises upper and lower electrodes which together define a tag location zone between them in which multiple tags can be placed. The lower electrode and the upper electrode are offset from each other such that they substantially do not overlap. This structure is used to sandwich tags vertically between two horizontally (laterally) offset reader electrodes. This enables power coupling and data transfer using capacitive coupling.

Abstract: An RF receiver (120) receives FSK-modulated bit streams on a carrier frequency, and adjusts its local oscillator (122) frequency to the carrier frequency by comparing the accumulated spread between the higher tone of the FSK signal and the frequency of the local oscillator to the accumulated spread of the lower tone of the FSK signal and the frequency of the local oscillator. In certain embodiments, this involves detecting zero-crossings (132) for I and Q signal pairs of the received FSK-modulated bit stream, and determining (218) positive occurrences of each zero-crossing of the I and Q signal pairs in one direction, and negative occurrences for each zero-crossing of the I and Q signal pairs in the opposite direction. Over a plurality of positive and negative occurrences, the total time elapsed between consecutive positive occurrences is measured and accumulated (134, 234) along with the total time elapsed between consecutive negative occurrences.

Abstract: A resonant converter (10) comprising a voltage compensation circuit (72, 73) configured to generate a periodic compensation voltage signal (Vslopecompens) at a switching frequency of the converter such that conduction intervals (31, 32) are ended according to first and second voltage levels in combination with the periodic compensation signal.

Abstract: A driver supplies an output voltage to an inductive load. The driver includes an input to receive a pulse width modulated control signal having a controllable duty cycle within a predetermined range. A first switch circuit receives a first switch signal to supply a first voltage, a second switch circuit receives a second switch signal to supply a second voltage, and the output voltage is the difference between the first voltage and the second voltage. An inverter and delay circuit receives the control signal to supply the first switch signal and the second switch signal being inverted and delayed with respect to each other. The delay of the delay circuit is selected to obtain an output voltage having a single polarity for each one of the controllable duty cycles within the predetermined range.

Abstract: A receiver for frequency down converting a radio frequency signal (10) using a multistage frequency (down) conversion. The radio frequency signal (10) having a center frequency that is comprised in one of at least two frequency bands, comprises oscillating means (20) for generating a first mixing signal (11) having a first frequency. And also a frequency divider (22) arranged to derive a second mixing signal (13) from the first mixing signal. The receiver further comprising a first mixer (12) arranged to down-convert the radio frequency signal (10) to a first lower frequency signal (15) using the first mixing signal (11) and a second mixer arranged to down-convert the first low frequency signal to a second lower frequency signal (18) using the second mixing signal (13). Wherein the division factor of the frequency divider and a ratio between the center frequency and the first frequency are determined by the one of at least two frequency bands.

Abstract: The invention is directed to a method for controlling a deceleration process of a DC motor (20), wherein the DC motor (20) is driven by a bridge driver (18) coupled to a power supply (12) intended to provide a supply voltage VDD at a power supply output (14), the method comprising the following steps: applying a deceleration PWM signal to the bridge driver (18) for decelerating the DC motor (20), and controlling the bridge driver (18) such that a motor-induced back current is reduced, if the voltage at the power supply output (14) exceeds a voltage threshold which is higher than VDD.