Abstract: A sigma-delta modulator (400) 400, 500, 600) for converting an input signal (X(s)) (X(s)) to a quantized output signal (Y(z)) (Y(z)), in which a feedback loop is provided between a filter (402) and a quantizer (403) of the modulator, the feedback loop configured to reduce quantization errors from the modulator by filtering and subtracting quantization noise fed back to an input of the quantizer (403).

Abstract: A signal processor for removing at least one unintended signal component from an input signal (ua) is proposed. The signal processor includes a filter device (130) and a processing device (150). The filter device (130) filters the input signal (uâ) and generates a filtered signal (uf), which includes the unintended signal component to be removed. The processing device (150) generates an output signal (um), which indicates a deviation of the input signal (ua) from the filtered input signal (uf). By detecting the unintended signal component first an removing this component from the input signal (uâ), the input signal will not be manipulated directly but the unintended signal component in the input signal (uâ) will be compensated. This allows to remove the unintended component from the input signal (uâ) with less distortions of the interesting components in the input signal (uâ).

Abstract: A wireless interconnect for an integrated circuit and a method of making the wireless interconnect. The interconnect includes a first antenna and a second antenna arranged over a plurality of electrically conductive interconnects. The interconnect also includes a propagation layer. The first and second antennae are arranged in between the propagation layer and the electrically conductive interconnects.

Abstract: An electronic circuit (1) comprises an input stage (2) and a driver stage (3). The input stage (2) comprises first, second, third and fourth inputs (In1-In4), and is configured to generate a first intermediate signal (Int1) which is the sum or the weighted sum of the first and third input signals (In1, In3), and a second intermediate signal (Int2) which is the sum or the weighted sum of the second and fourth input signals (In2, In4). The driver stage (3) comprises an output (OUT), is configured to generate an output signal (6) present at the output (OUT), and is configured to directly compare the first and second intermediate signals (Int1, Int2) such that the output signal (6) indicates which of the two intermediate signals (Int1, Int2) is larger.

Abstract: The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacity hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.

Abstract: A receiver to receive a signal associated with a low-density parity-check (LDPC) code. The receiver includes a memory device, an address generator, and an LDPC decoder. The LDPC decoder includes a row designator and a position designator. The memory device stores data related to an LDPC decoding process. The address generator generates an access address to the stored data. The LDPC decoder performs the LDPC decoding process. The row designator designates a row from a parity-check matrix as a parent row and designates a plurality of corresponding rows from the parity-check matrix as child rows. The position designator designates an original position order of each parent non-zero element of 10 the parent row according to an actual position order of each parent non-zero element in the parent row. The actual position order includes a numerical order of the parent non-zero elements.

Abstract: An ADC is disclosed which has, as a first stage, a successive approximation converter, or other compensated, direct comparison converter, followed by a sigma delta modulation converter as a second stage. The sigma delta converter may beneficially be a first order modulator. The resulting ADC combines accuracy with low power consumption per conversion, and thus is particularly suited for use in temperature sensors for applications such as RFID transponders. Such a temperature sensor and an RFID transponder are also disclosed. There is also disclosed a method of analog-to-digital conversion, comprising a first successive approximation register or other compensated, direct comparison conversion stage followed by a sigma delta modulation stage, which, further, may be combined with providing a proportional-to-absolute-temperature (PTAT) signal, for low-power, accurate temperature sensing.

Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing at least two members (10, 11, 16) comprising electrically conductive material; providing a microelectronic device (15); placing the electrically conductive members (10, 11, 16) and the microelectronic device (15) in predetermined positions with respect to each other, and establishing electrical connections between each of the electrically conductive members (10, 11, 16) and the microelectronic device (15); and providing a non-conductive material for encapsulating the microelectronic device (15) and a portion of the electrically conductive members (10, 11, 16) connected thereto. The electrically conductive members (10, 11, 16) are intended to be used for realizing contact of the microelectronic device (15) arranged inside the package (1) to the external world.

Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.

Abstract: A semiconductor device eg. a MOSFET (1) comprising a substrate (40) including a first region (18) and a second region (16) of a first conductivity type and a third region (42) between the first and second regions of a type opposite to the first conductivity type, and being covered by a dielectric layer (20), a plurality of trenches (12) laterally extending between the third and second region, said trenches being filled with an insulating material, and being separated by active stripes (14) comprising a doping profile having a depth not exceeding the depth of the trenches wherein each trench terminates before reaching the dielectric layer (20),namely is separated from the third region by a substrate portion (26) such that the respective boundaries between the substrate portions and the trenches are not covered by the dielectric layer. A method for manufacturing such a semiconductor device is also disclosed.

Abstract: A system implements a secure transaction of data between a server and a remote device. The remote device comprises: processing means adapted to process input data according to a security process; data storage means adapted to store verification information derived from the input data according to an encryption algorithm; and communication means for communicating the input data which has been processed by the security process to the server. The server is adapted to transmit a verification request to the remote device, and to verify the integrity of the security process based on verification information received from the communication means of the remote device in response to the verification request.

Abstract: A container (100) is disclosed comprising a compartment (110); a controller (120) for controlling access to the compartment (110); a near-field communication device (130) for providing the controller (120) with identification information, said controller (120) being responsive to said identification information, wherein the near-field communication device (130) comprises a plurality of antennae (132), each of said antennae being accessible in a different surface area of the container (100). The container (100) may be used in games using near-field communication (NFC) technology, such as a NFC-based version of pass the parcel. An electronic game system (300) comprising such a container and a game controller (200) for use in such an electronic game system (100) are also disclosed.

Abstract: The present invention discloses a programmable device (10) comprising a controller (14) for processing a sequence of program instructions to control the programmable device; and a near field communication device (12) for retrieving the program instructions from at least one transmission tag (24) and for providing the controller (14) with the retrieved sequence of program instructions. In an embodiment, the controller (14) is arranged to receive individual instructions from respective transmission tags (24). This facilitates the programming of the device (10) by means of instruction-carrying transmission tags, which, amongst others, allows for easy programming of programmable toys such as robots.

Abstract: A system and method for processing data utilizes a matrix of processing units using an array of commands stored in memory to process input data words to generate output data words, which can be used in various applications.

Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remo

Abstract: A visual prosthesis implant (1) is provided which comprises an SIMD-based processor array (6) adapted for receiving image signals from an image sensor (5) and outputting processed signals, and a bio-compatible electrode implant (7) receiving the processed signals and adapted for coupling to neurons. Using the SIMD-based processor array (6) provides high performance at small power dissipation and small chip area such that a fully implantable is visual prosthesis is achieved.

Abstract: A method of calibrating a pipelined analog to digital converter (400) having a plurality of DAC elements (410) and an additional calibration DAC element (420), in which a combination of positive, negative and zero reference voltages to the element under calibration and positive and negative reference voltages to the additional calibration DAC element to obtain four calibration states from which an error of the element under calibration is extracted by calculating an average of the difference between the four calibration states.

Abstract: An edge rate suppression circuit arrangement is provided for operation with an open drain bus. The circuit arrangement includes a variable resistive circuit having an input for receiving a variable voltage signal and an output coupled to the open drain bus, and a control circuit configured to operate the variable resistive circuit. The control circuit operates the variable resistive circuit in respective high and low resistance states in response to the variable voltage signal.

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: An amplifier circuit, comprising a differential input stage (M1, M2), two cross-coupled current mirrors (M3, M4; M5, M6) coupled to respective outputs of the differential input stage (M1, M2), and a minimum selector circuit (M11, M12, M13, M14) coupled to outputs of the current mirrors.