Abstract: Consistent with an example embodiment, there is a semiconductor component comprising a semiconductor chip made of a doped silicon substrate. The chip is doped into a semiconductor device and structured, and includes an inner connection metallization in a contact window. The inner connection metallization of said semiconductor chip is connected to the respective outer connection metallization by a wire bond connection, wherein the inner connection metallization comprises a reinforcing system having an open grid structure on the doped silicon substrate.

Abstract: A counter circuit and method of controlling such a counter circuit, including a first counting section that counts in accordance with a state-cycle, and a second counting section clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.

Abstract: A MEMS piezoresistive resonator (8, 78) is driven at a higher order eigenmode (32) than the fundamental eigenmode (31). The route of flow of a sense current (22) is arranged in relation to a characteristic of the higher order eigenmode (32), for example by being at a point of maximum displacement (50) or at a point of maximum rate of change with respect to distance (x) of displacement of the higher order eigenmode (32). The route of flow of the sense current (22) may be arranged by fabricating the MEMS piezoresistive resonator (8, 78) with a trench (15) formed between two beams (11, 12) of the MEMS piezoresistive resonator (8, 78), the end of the trench being located at the above mentioned position.

Abstract: A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link (110), such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device (120) coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

Abstract: A method for detecting a delimiter pattern (SOF) in a signal stream containing a carrier or subcarrier modulated by the delimiter pattern comprises: specifying an expected delimiter occurrence time (t1) of an occurrence of the delimiter pattern and a tolerance zone (tz) within which the expected delimiter occurrence time (t1) may jitter; approximating, within the tolerance zone (tz), a zero of a cross correlation function (CCF) of the data stream with the delimiter pattern, or detecting the phase (?) of the carrier or subcarrier in respect to an arbitrarily defined reference position within the tolerance zone (tz), e.g.

Abstract: Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarizing. During the planarizing the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.

Abstract: Reference magnetic elements or bits with a range of magnetic volumes smaller than the minimum size used for actual data storage are written or patterned in the data storage device. The reference elements or bits have dimensions such that their magnetization will relax in a shorter time than that of the minimum expected relaxation time of the storage elements or bits. Probing of the magnetization of the reference elements or bits allows the detection of the probable onset of magnetization relaxation in the storage elements or bits therefore signaling that the re-writing (re-magnetizing) of the storage elements or bits is necessary. Such a scheme can be organized over rows, columns, or sectors.

Abstract: A method of manufacturing a semiconductor device based on a SiC substrate involves forming an oxide layer on a Si-terminated face of the SiC substrate at an oxidation rate sufficiently high to achieve a near interface trap density below 5×1011 cm?2; and annealing the oxidized SiC substrate in a hydrogen-containing environment, to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET having improved inversion layer mobility and reduced threshold voltage. It has been found that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. The deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.

Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element 14. A sacrificial layer 20 is provided over the device element and a package cover layer 24 is provided over the sacrificial layer. A spacer layer 13 is formed over the sacrificial layer and is etched to define spacer portions adjacent an outer side wall of the sacrificial layer. These improve the hermetic sealing of the side walls of the cover layer 24.

Abstract: The invention relates to an electrical circuit arrangement comprising a plurality of reconfigurable circuit cells, each reconfigurable circuit cell comprising —a plurality of nodes, —a plurality of links connectable to the nodes, —at least one circuit element, wherein the reconfigurable circuit cells are each configured to form either a node or a link of the electrical circuit arrangement.

Abstract: A program is executed with a first programmable device (10). Device operating points such as power supply voltage and/or clock frequency are adapted dependent on the states reached by the device during execution. Operation of programs that may have been sold after the device has been supplied to users is optimized by executing the computer program on each of a plurality of programmable devices (10) like the first programmable device, and collecting statistical data associated with the execution states encountered during execution by the plurality of programmable devices (10). Each of the plurality of programmable devices (10) collects its own statistical data and uploads the collected information to a common profiling apparatus (14). The profiling apparatus assigns device operating points to respective ones of the execution states, using an optimization that depends on the combined statistical data from the plurality of programmable devices (10).

Abstract: The invention relates to a semiconductor device for use in a stacked configuration of the semiconductor device and a further semiconductor device. The semiconductor device comprises: a substrate (5) comprising at least part of an electronic circuit (7) provided at a first side thereof. The substrate (5) comprises a passivation layer (19) at the first side and a substrate via that extends from the first side to a via depth beyond a depth of the electronic circuit (7) such that it is reconfigurable into a through-substrate via (10) by backside thinning of the substrate (5). The semiconductor device further comprises: a patterned masking layer (15) on the first side of the substrate (5). The patterned masking layer (15) comprises at least a trench (16) extending fully through the patterned masking layer (15). The trench has been filled with a redistribution conductor (20). The substrate via and the redistribution conductor (20) comprise metal paste (MP) and together form one piece.

Abstract: A system and method provide adaptive filtering of radio frequency (RF) signals. Multiple signals are received in a predetermined RF spectrum, the signals including a desired signal and multiple potentially interfering signals. A first signal of the potentially interfering signals is down-converted to a baseband signal, and a power of the baseband signal is determined. When the power exceeds a predetermined threshold power, a first notch filter, corresponding to a frequency of the first signal, is activated.

Abstract: The invention relates to a method and a device to detect thin lines of an incoming signal, especially of an image or video signal, comprising the steps of: analysing the incoming signal, calculating the first derivative of the incoming signal (52), analysing and marking the crossing of zero of the fust derivative (53), analysing the direction of the zero crossing (54) and coding the direction into the zero-signal, eliminating noise and invalid alternating sequences to identify the existence of a thin line.

Abstract: The invention relates to a method of determining a charged particle concentration in an analyte (100), the method comprising steps of: i) determining at least two measurement points of a surface-potential versus interface-temperature curve (c1, c2, c3, c4), wherein the interface temperature is defined as a temperature of the interface between a measurement electrode and the analyte (100), wherein the surface-potential is defined at the interface, and ii) calculating the charged particle concentration from locations of the at least two measurement points of said curve (c1, c2, c3, c4).This method, which still is a potentiometric electrochemical measurement, exploits the temperature dependency of a surface-potential of a measurement electrode. The invention further provides an electrochemical sensor and electrochemical sensor system for determining a charged particle concentration in an analyte. The invention also provides various sensors which can be used to determine the charged particle concentration, i.e.

Abstract: A digital electronic device is provided which comprises a digital clock deviation detecting means and a digital clock correcting means. The clock deviation detecting means is used to detect a deviation of a first clock signal of the electronic device and/or the duty cycle of the first clock signal. The clock correcting means is used to correct the first clock signal and/or the duty cycle of the first clock signal if the clock deviation detecting means has detected a deviation of the first clock signal and/or the duty cycle of the first clock signal. The clock correcting means comprises at least a first and second compensation path (P1, P2) for compensating deviations in the first clock signal and/or the duty cycle thereof, when the first clock signal passes through the first or second path. The first path (P1) does not induce a compensation and is selected if the clock deviation detecting means has not detected a deviation in the first clock signal.

Abstract: Clear channel assessment (CCA) is a very important issue in Ultra-Wideband (UWB) systems. An effective CCA mechanism will have a large impact on the overall throughput of the communications system. It is disclosed methods and circuits to carry out CCA determinations exploiting the structure of the pulse signal either by using a moving average or by performing a cross-correlation with a locally generated signal.

Abstract: A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized “hot spot” is obtained.

Abstract: A thin-film bulk acoustic wave (BAW) resonator, such as SBAR or FBAR, for use in RF selectivity filters operating at frequencies of the order of 1 GHz. The BAW resonator comprises a piezoelectric layer (14) having first and second surfaces on opposing sides, a first electrode (16) extending over the first surface, and a second electrode (12) extending over the second surface, the extent of the area of overlap (R1) of the first and second electrodes determining the region of excitation of the fundamental thickness extensional (TE) mode of the resonator. The insertion loss to the resonator is reduced by providing a dielectric material (18) in the same layer as the first electrode (16) and surrounding that electrode. The material constituting the dielectric material (18) has a different mass, typically between 5% and 15%, from the material comprising the first electrode (16) it surrounds. The mass of the dielectric material (18) can be lower or higher than the mass of the first electrode (16).

Abstract: A biocompatible electrode is manufactured by depositing filling metal 36 and etching back the filling metal to the surface of the surrounding insulator 30. Then, a further etch forms a recess 38 at the top of the via 32. An electrode metal 40 is then deposited and etched back to fill the recess 38 and form biocompatible electrode 42. In this way, a planar biocompatible electrode is achieved. The step of etching to form the recess may be carried out in the same CMP tool as is used to etch back the filling metal 36. A hydrogen peroxide etch may be used.