Abstract: The present invention provides a method of lithographic patterning. The method comprises: applying to a surface to be patterned a photoresist (18) comprising a polymer resin, a photocatalyst generator which generates a catalyst on exposure to actinic radiation, and a quencher; exposing the photoresist (18) to actinic radiation through a mask pattern (12); carrying out a post-exposure bake; and then developing the photoresist (18) with a developer to remove a portion of the photoresist which has been rendered soluble in the developer. Either the polymer resin is substantially insoluble in the developer prior to exposure to actinic radiation and rendered soluble in the developer by the action of the catalyst, and by the action of the quencher during the bake, or the polymer resin is soluble in the developer prior to exposure to actinic radiation and rendered substantially insoluble in the developer by the action of the catalyst, and by the action of the quencher during the bake.

Abstract: Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.

Abstract: A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.

Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1).

Abstract: A vertically oriented self terminating semiconductor device such as a discrete trench MOS device (10, 38) that includes a cylindrical drift region (18) that extend downward from a surface region to a substrate (11) and a dielectric region (20) that exponentially tapers outward from the cylindrical drift region as the drift region approaches the substrate. A field plate electrode (12) is disposed on the dielectric region. Alternatively, the gate electrode (40, 46) may be disposed on the dielectric region, optionally with an underlying field plate electrode (48).

Abstract: A carrier (100) for bonding a semiconductor chip (114) onto is provided, wherein the carrier (100) comprises a die pad (101) and a plurality of contact pads (102), wherein each of the plurality of contact pads (102) comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (109), a first buffer layer, and a first conductive layer (108). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer (109) into the first conductive layer (108), and at least two of the contact pads (102) has an ultrafine pitch relative to each other.

Abstract: The invention relates to an electronic device provided with an electronic component which comprises an integrated circuit arrangement including a semiconducting substrate, active components, and passive components such as capacitors and resistors. The resistors comprise materials of a high resistivity and can be manufactured with resistance values which lie within a narrow tolerance range. The invention further relates to a transmitter, a receiver, an electronic component, a peripheral circuit, a current supply circuit, a filter module, and an integrated circuit arrangement.

Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.

Abstract: A variety of near-field devices, methods and systems are implemented in various fashions. One implementation is directed to a mobile station (102) with an over-the-air (OTA) transceiver (104) for communication with a trusted service manager. The mobile station also has a near-field communications transceiver (112) for communication with a terminal reader using file-identifiers of a first size. A memory (106) is used for storing files arranged according to two different sets of files, the first set of files identified by file-identifiers of a first size and the second set of files identified by file-identifiers of a second size that is a different size from the first size. A processor (108) provides access by the OTA transceiver (104) to the stored files. Access by the near-field communications transceiver (112) is provided to the stored files by running either a Java-based emulator for accessing the first set of files or Java APIs to access the second set of files.

Abstract: Packaged semiconductor product (2) including a first semiconductor device (4A) and a packaging structure with a protective envelope (6) and a first and second external electrode (8,10). The first semiconductor device (4A) has a first substrate (11A) and is provided with a first passivation layer (12A) and a first electronic structure. The first substrate has a first main surface (14). The first substrate (11A) is embedded in the protective envelope (6) and the first main surface (14) faces a first opening (23) of the protective envelope (6). The first electronic structure has a first and a second contact region (20, 22) for electrically contacting the first electronic structure. The first passivation layer (12A) substantially covers the first main surface (14) and the first electronic structure. The protective envelope (6) extends between the first passivation layer (12A) and the first external electrode (8) towards the first contact region (20).

Abstract: The invention relates to an semi-conductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.

Abstract: The present invention relates to a method of manufacturing a solid-state battery with a high flexibility. The method comprises the steps of: forming an arrangement of battery cells (2) on a first substrate layer and providing a barrier layer (5) between the battery cells and the first substrate layer, applying on the arrangement of battery cells on the side not covered by the first substrate layer a second substrate layer (13), and removing the first substrate layer completely from the barrier layer, applying on the barrier layer a third substrate layer (14). The present invention further refers to the solid-state battery manufactured according to the method, as well as to a device, including the solid-state battery.

Abstract: A loudspeaker drive circuit comprises a signal path compressor/limiter (12) for implementing a change to the peak-mean amplitude ration in the time domain. A feedforward control loop measures an acoustic quality of the signal at the output of a control loop compressor/limiter (20) or the output of the signal path compressor/limiter (12), and also estimates a loudspeaker excursion based on the signal at the output of the control loop compressor/limiter (20). The signal path compressor/limiter is controlled based on the acoustic quality measurement and excursion estimation. The invention provides a method for the maximisation of the acoustic output of a loudspeaker by adjusting the characteristics of a compressor/limiter, with the constraint that the audio quality stays acceptable, and that the diaphragm displacement does not exceed a certain threshold.

Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire located in an interconnect layer of said semiconductor device, the at least one wire having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.

Abstract: A GPS RF front-end is disclosed comprising an antenna for receiving GPS signals, an analog to digital converter for sampling received GPS signals and interface circuitry for outputting the GPS signal samples. The GPS RF front-end is configured to vary the sample resolution of GPS signal samples outputted. Also disclosed is a corresponding method of providing a position fix, storage medium and apparatus for the same.

Abstract: The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).

Abstract: A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.

Abstract: A variety of circuits, methods and devices are implemented for radiofrequency amplifiers. According to one such implementation, a radiofrequency amplifier circuit is implemented in a SMD package. The circuit amplifies a radiofrequency signal having a base-band portion and a plurality of carrier signals frequency-spaced larger than the base-band bandwidth. The circuit includes a radiofrequency transistor connected to a circuit output having a parasitic output capacitance. The source-drain terminal is electrically connected to the circuit output. An internal shunt inductor provides compensation for the parasitic output capacitance. A high-density capacitor is connected between the internal shunt inductor and a circuit ground. The high-density capacitor has a terminal with a surface area can be at least ten times that of a corresponding planar surface.

Abstract: The present invention relates to a sensor comprising a substrate (10) carrying a field effect transistor (30) having a gate electrode (32), the sensor further comprising a measurement electrode (36) spatially separated from the gate electrode; and a reference electrode (40), said measurement electrode being in configurable conductive contact with said gate electrode, the sensor further comprising a charge storage element (60) comprising a first electrode connected to a node (38) between the measurement electrode and the gate electrode; and a second electrode configurably connected to a known potential source (80). The present invention further relates to a method of performing a measurement with such a sensor.