Abstract: In a power amplification circuit an output signal is generated by combining the power of a first and second signal that have been amplified separately. An input signal is received that indicates a desired amplitude and phase of the output signal. A controllable phase shift circuit adapts the phase of first and second signals dependent on the desired amplitude, so that, when the signals with the adapted phases are combined, the resulting output signal will have an envelope with the desired amplitude. A time dependent common mode phase shift is applied to both the first and second signal. A control circuit selects the time dependent common mode phase shift as a function of the desired amplitude of the output signal, to compensate for envelope amplitude dependence of a common phase shift introduced by the amplification.

Abstract: An audio comparison method and apparatus compares audio streams by measuring the times of volume peaks in the audio streams and identifying correlations between the peaks in the audio streams, subject to possible delay between the streams. The audio comparison allows the identification of audio streams including the same audio content even in the presence of delay and distortion and using low processing power. The audio comparison has particular application in car radios to allow automatic retuning.

Abstract: A circuit comprising a power factor correction stage having a DC input, a ground input, a DC output and a ground output; a capacitor; a diode; and discharge means. A first terminal of the diode is connected to an input of the power factor correction stage, a second terminal of the diode is connected to the first plate of the capacitor; and the second plate of the capacitor is connected to the other input of the PFC stage. The discharge means is connected to the capacitor and is configured to discharge the capacitor such that it contributes to the output of the PFC stage when the level of a signal at the input of the PFC stage falls below a threshold value.

Abstract: The invention relates to an electromechanical transducer (100). The electromechanical transducer (100) comprises a cantilever beam (101) and an excitation unit (102) that is adapted for exciting a motion of the cantilever beam (101). A detection unit (103) is adapted for detecting an electrical signal (iout) in response to the excited motion of the cantilever beam (101).

Abstract: The present invention relates to a tilt correction method and a corresponding apparatus for correcting tilt of RF signals in a wanted channel having a predetermined frequency range, in a signal path of a communication equipment, wherein the RF signals are down-converted to an intermediate frequency of an IF domain. The method comprises the steps of: providing a predetermined RF signal having a particular frequency to the signal path, detecting an output signal in the intermediate frequency (IF) domain and outputting a detection result, repeating the providing step and the detecting step for plural RF signals of different frequencies within the channel frequency range, determining the tilt of the RF signals in the frequency range by comparing the detection results, and correcting the tilt to obtain a minimized tilt of the wanted channel depending upon the determined tilt.

Abstract: A sensor senses a magnitude of a physical parameter of the sensor's environment. The sensor has first and second electrodes, and a material layer between them. The material has an electrical property, e.g., capacitance or resistance, whose value depends on the magnitude of the physical parameter. The first electrode is formed in a first layer, and the second electrode is formed in a second layer, different from the first layer. The first layer has a trench and an elevation next to the trench. The trench has a bottom wall and a side wall. The material is positioned on the bottom wall and on the side wall and on top of the elevation. The trench accommodates at least a part of the second electrode. The second electrode leaves exposed the material formed on top of the elevation.

Abstract: An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Abstract: A power factor correction stage comprising: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a first converter stage and one or more further converter stages, wherein each of the converter stages is connected to the input terminal and the output terminal, and each converter stage comprises a switch; and a controller configured to operate the switches of the converter stages. The controller is configured to operate the switch of the one or more further converter stages at a period of time after operation of the switch of the first converter stage for a current switching cycle, wherein the period of time corresponds to a proportion of the switching frequency for an earlier switching cycle that does not correspond to substantially the period of the earlier switching cycle divided by the number of converter stages.

Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

Abstract: According to a first aspect of the present invention there is provided a signal generation system for generating a predetermined analog signal. The system comprises a clock generator (1) adapted for generating on the basis of an external clock signal a predetermined clock signal, a signal generator including a first gain stage (21) and a second gain stage (22) adapted for providing an overall gain of the signal generator and outputting a stepped analog signal, an analog filter (23) adapted for filtering the stepped analog signal output by the second gain stage and for outputting the predetermined analog signal, and a first and a second clock mapping units (3,4) adapted for receiving the predetermined clock signal, and respectively supplying to the first and second gain stages non-overlapped clock signal, wherein the amount of gain provided by the first and second gain stages is controlled by the non-overlapped clock signals.

Abstract: This invention relates to improved methods of preventing MOSFET damage in a resonant switched mode power converter (1) by preventing or limiting capacitive mode operation. A combination of response actions (respectively delaying MOS-FET switch-on, adjusting switching phase, forcing a switch-on, and increasing frequency) is utilised. In the preferred embodiment, the voltage slope at the half-bridge node (5) is monitored, and in alternative embodiments the same or similar set of response actions is triggered by monitoring different signals, including: the resonant current polarity at switch-off or after the non-overlap time; the voltage of the to-be-switched-on” switch; and the voltage of the “just-switched-off” switch.

Abstract: In a method for manufacturing an electronic device an integrated circuit (1) is arranged between two layers (2, 3) of a substrate, said integrated circuit (1) having at least one contacting surface, a hole (4) is formed in at least one substrate layer (3) above said at least one contacting surface, a conductive structure (5) is formed on a surface of said at least one substrate layer (3) facing away from the integrated circuit (1) and said conductive structure (5) is connected to said contacting surface by means of said hole (4).

Abstract: Methods and systems directed toward a PLL circuit (100) including a local lock detector (180) receiving an error signal and providing a lock signal, and a charge pump (120) for receiving the error signal and providing a charge signal. A loop filter provides a first loop filter bandwidth and a second loop filter bandwidth. The loop filter includes a first low-pass filter (130) configured to receive the charge and lock signals, alter a filter characteristic in response to the lock signal, and provide a first filter signal. The loop filter includes a second low-pass filter (150) configured to receive the first filter and lock signals, alter a filter characteristic in response to the lock signal, and provide a loop filter signal. The PLL circuit includes a VCO (160) for receiving the loop filter signal and providing an output signal, and a divider (170) for receiving the output signal and dividing it to provide the reference signal.

Abstract: Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNxHy, wherein x>1.33 and y>0. A method of forming such a device is also disclosed.

Abstract: A magnetoresistive angular sensor and sensing method, in which an external magnetic field generator is used to provide a first mode in which a dc external magnetic field is provided in a predetermined direction and which dominates over the magnetic field generated by the input device being sensed. In a second mode, the external magnetic field is smaller. The angular sensor arrangement outputs from the two modes are combined, and this enables the input device angular orientation to be determined with offset voltage compensation.

Abstract: An MR sensor arrangement is integrated with an IC. A metal layer of the IC structure (e.g. CMOS) is patterned to define at least first and second contact regions. Metal connecting plugs are provided below the first and second contact regions of the metal layer for making contact to terminals of the integrated circuit. A magnetoresistive material layer is above the metal layer and separated by a dielectric layer. Second metal connecting plugs extend up from the metal layer to an MR sensor layer. The sensor layer is thus formed over the top of the layers of the IC structure.

Abstract: A method for providing fast and secure access to MIFARE applications installed in a MIFARE memory (MM) being configured as a MIFARE Classic card or an emulated MIFARE Classic memory, comprises: keeping a repository (5) of MIFARE memories (MM) and user identifications (UID) assigned to said MIFARE memories (MM) as well as of all MIFARE applications installed in the MIFARE memories (MM), wherein, when a new MIFARE application (TK2) is to be installed in a MIFARE memory (MM) identified by a user identification (UID) the present memory allocation of said MIFARE memory (MM) is retrieved, an appropriate sector (S) of said MIFARE memory (MM) is calculated, a key (K) is calculated for said MIFARE application (TK2) and the MIFARE application (TK2) together with the assigned sector (S) and key (K) are linked to the user identification (UID) and are stored in the repository (5).

Abstract: The present invention proposes a control loop for receiving a reference signal r(t) and generating an output signal c(t) based on the reference signal r(t). The control loop comprises a subtracting element(320), a correcting element(330,350), a control path(340) and a storage element(360). The subtracting element(320) generates a difference signal d(t) including a difference between the reference signal r(t) and the output signal c(t). The correcting element (330,350) generates an adjusting signal b(t) based on the difference signal d(t). The control path(340) generates the output signal c(t) based on the adjusting signal b(t). And the storage element (360) stores at least one internal state of at least the correcting element(330,350) and applies the stored internal state to at least the correcting element(330,350) based on an instruction signal i(t).

Abstract: A system and method for providing fault detection capability is provided which comprises a first node (2). The first node (2) comprises a first processing subsystem (5) generating data (14) to be transmitted. The first node (2) has a fault supervisor unit (13) adapted to gather and process fault indications arising in the first node (2). The first processing subsystem (5) and the fault supervisor unit are both integrated in the first node (2). The first node (2) is structured such that, when no fault indications are detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a first key (15) as a validity key, and, when at least one fault indication is detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a second key (16) as the validity key, and the data (14) to be transmitted are encrypted by overlaying the respective validity key (15; 16) on the data.

Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).