Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: A novel Si MEMS piezoresistive resonator is described. The resonator has a shape of a frame, such as a ring or a polygon frame, which has two or more anchors. Electrodes located at the outer or inner rim of the resonant structure are used to excite the structure electrostatically into resonance with a desired mode shape. One or plurality of locally doped regions on the structure is used for piezoresistive readout of the signal. In the most preferred embodiments, the structure is a ring, which has four anchors, two electrodes and four piezoresistive regions at different segments of the structure. The piezoresistive regions are alternatively located at the outer rim and inner rim of the structure in such a way that the piezoresistive signals of the same sign from different regions can be collected. Advantages of this device are large readout signal, large electrode area, robustness, suppressed out-of-plane vibration and larger usable linear range.

Abstract: A Static Random Access Memory comprising a matrix arrangement of cells, each cell comprising:—a bistable loop of a first inverter and a second inverter, in which an input of the first inverter is coupled to an output of the second inverter at a first bistable node and an input of the second inverter is coupled to an output of the first inverter at a second bistable node;—a first access transistor connected between the first bistable node and a write bitline, the first access transistor having a control terminal connected to a write wordline, and—a second access transistor connected between the second bistable node and a line being the complement of the write bitline, the second access transistor having a control terminal connected to the write wordline wherein—a first separate read port is connected between a read bitline and a source potential, which first read port has at least two control terminals, one control terminal being connected to the second bistable node and one to a read wordline, and—a second se

Abstract: Data is received with a transceiver circuit with a receiver branch (14) that comprises a notch filter (140) and a digital Fourier transformer (146). Furthermore the transceiver circuit has a transmitter branch (16) comprising an inverse digital Fourier transformer (160). Prior to reception the transceiver circuit is switched to a calibration mode, wherein an output of the transmitter branch (16) is coupled to an input of the notch filter (140). The inverse digital Fourier transformer (160) of the transmitter is used to compute an inverse transform of a spectrum with a frequency component at a selected position. A signal derived from the inverse transform is applied to an input of the notch filter (140) in the calibration mode. The digital Fourier transformer (146) is used to Fourier transform an output signal of the notch filter (140). A control setting of the notch filter to suppress the frequency component from an output of the digital Fourier transformer (146) is determined.

Abstract: A membrane for an acoustic transducer is provided which comprises a first portion having a first stiffness, and a second portion comprising a first subsection having a second stiffness and a second subsection having a third stiffness, wherein the second stiffness and the third stiffness are different.

Abstract: The invention relates to a method of determining a charged particle concentration in an analyte (100), the method comprising steps of: i) determining at least two measurement points of a surface-potential versus interface-temperature curve (c1, c2, c3, c4), wherein the interface temperature is obtained from a temperature difference between a first interface between a first ion-sensitive dielectric (Fsd) and the analyte (100) and a second interface between a second ion-sensitive dielectric (Ssd) and the analyte (100), and wherein the surface-potential is obtained from a potential difference between a first electrode (Fe) and a second electrode (Se) onto which said first ion-sensitive dielectric (Fsd) and said second ion-sensitive dielectric (Ssd) are respectively provided, And ii) calculating the charged particle concentration from locations of the at least two measurement points of said curve (c1, c2, c3, c4).

Abstract: A microphone system is provided, wherein the microphone system comprises a microphone array comprising a plurality of microphone units each adapted to generate a primary signal indicative of an acoustic wave received from the respective microphone unit, a first echo cancellation unit, an integrator unit, and a combination unit, wherein the microphone system is adapted to generate a first dipole response and a monopole response from the primary signals, wherein the integrator unit is adapted to generate a first integrated dipole response by integrating the first dipole response, wherein the first echo cancellation unit is adapted to generate a first echo cancelled integrated dipole response from the first integrated dipole response, and wherein the combination unit is adapted to combine the monopole response and the first echo cancelled integrated dipole response.

Abstract: A microelectronic package assembly comprises a lead frame having a holding bar (16) and a microelectronic package (14). The microelectronic package (14) comprises a package body (22) and a connecting element (24) for connecting the package body (22) to the holding bar (16) of the lead frame (12). The connecting element (24) extends from an outer surface (26) of the package body (22) and is engaged with an ending part (28) of the holding bar (16).

Abstract: A processor (10) of processes data using a cache circuit (12). The processor (20) is coupled to a functionally detachable device (19) via the cache circuit (12). When a cache line is loaded into cache memory (120), it is tested whether the cache line has an address within a detachable device address range allocated to the detachable device (19). If so, identification of the cache line, or a range of addresses that includes the address of the cache line is stored. When a flush command is received that requires write back cached data to the detachable device, the identification is used to select the cache line for selective write back to the detachable device. Thus less cache data needs to be invalidated when a device is functionally detached from the circuit.

Abstract: Data such as image, sound or other media content is delivered between peer devices over a dedicated peer-to-peer communications medium. According to an example embodiment, data is communicated between peer devices respectively belonging to one of a plurality of device classes respectively identified by a device-class identification (ID). Data is stored to identify communications that are to be carried out between devices having respective IDs, such that each pair of IDs has predefined execution steps based upon operational status of the devices. Based upon the device-class ID pair of two peer devices and an operating status of one or both devices, the devices automatically select and execute a communications approach to communicate data therebetween. This communication can be effected in response to a simple user input (e.g., which is specific to neither data nor transfer direction).

Abstract: A sensor device (100, 2800) for detecting particles, the sensor device (100, 2800) comprising a substrate (102), a first doped region (104) formed in the substrate (102) by a first dopant of a first type of conductivity, a second doped region (106, 150) formed in the substrate (102) by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region (108) at a junction between the first doped region (104) and the second doped region (106, 150), a sensor active region (110) adapted to influence a property of the depletion region (108) in the presence of the particles, and a detection unit (112) adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region (104) and the second doped region (106, 150), the electric measurement being indicative of the presence of the particles in the sensor active region (110).

Abstract: The invention relates to an integrated Doherty amplifier with an input network connecting the input to the main stage and to the peak stage, and with an output network connecting the main stage and the peak stage to the output. The output network has a shunt capacitor to signal-ground in parallel to a parasitic capacitance of the main stage, and has a shunt inductor between the main stage and signal ground. The shunt configuration enables to use the MMIC Doherty amplifier in a wide frequency range. At least some of the inductors of the input network and/or output network are implemented using bond wires. Their orientations and locations provide minimal mutual electromagnetic coupling between the wires and the return RF current paths.

Abstract: A device for use in electronic article surveillance EAS is disclosed which comprises a resonant circuit, typically designed for 8.2 MHz operation, in addition to a transponder, such as RFID, for non-contact communication with a communication station. The RFID transponder can provide a signal to detune the resonant circuit to disable the EAS and optionally another signal to tune or retune the resonant circuit to enable or re-enable the EAS. The detuning and tuning or retuning may preferably be achieved using phase change memory material, configured as a programmable switch having two states with different resistances.

Abstract: This invention relates to a method, a computer program product, a device, and a system, wherein a receiver unit (200,300,300?,500,500?,600,600?) is configured to operate in a single-channel mode and in a multi-channel mode, wherein in the single-channel mode the receiver unit (200,300,300?,500,500?,600,600?) is configured to output exactly one channel of a received signal, and in the multiple-channel mode the receiver unit (200,300,300?,500,500?,600,600?) is configured to output at least two channels of the received signal.

Abstract: The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M1) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M1) in a circuit having a very thin gate oxide, produced by a deep sub micron process, a circuit arrangement is proposed for controlling a high side CMOS transistor (M1), wherein the high side CMOS transistor (M1) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M1) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference (11) having a capacitor (C1), which is charged for switching on and discharged for switching off the high side CMOS transistor (M1).

Abstract: A power island for a system-on-a-chip (SoC) includes a first segment, a second segment, and a supply line. The first segment includes a hardware device and operates the hardware device at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic and operates the scalable logic at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal (VDD) and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics.

Abstract: The invention relates to a circuit arrangement (30, 40, 70, 80, 90) of a low-noise linear input amplifier comprising a parallel circuit of a common-base circuit (20) and a common-emitter circuit (30), the emitters of two first transistors (Q3, Q4) are interlinked and the bases of two second transistors (Q1, Q2) are intercoupled, the collectors are interconnected in parallel with the output, and the source voltage (VG) is interlinked with the emitters of the second transistors (Q1, Q2) and with the bases of the first transistors (Q3, Q4), in which a linearization of the output current (OUTLNA1,2) as a function of the source voltage (VG) is achieved by a linearization of the transfer function, such as the tangential hyperbolic function, of the first and second transistors (Q1, Q2, Q3, Q4).

Abstract: A method of streaming data from a server (S) at a server data rate (Cs) via a network to at least one terminal at a terminal reception data rate (Crec) is provided. A streaming section from the server (S) is requested by the terminal (T). Streaming data is forwarded from the server (S) to the network (N) at a server data rate (Cs) and from the network (N) to the terminal (T) at a reception data rate (Crec). Data received from the network (N) is buffered in the terminal buffer (AL) for at least a first period. The rendering of the buffered data is initiated after the first period at a first rendering rate (Cren), which is lower than the server data rate (Cs) or the reception data rate (Crec). The first rendering data rate (Cren) is adapted according to the filling of the terminal buffer (AL) with received streaming data until the rendering data rate (Cren) corresponds to the server data rate (Cs).

Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (14). A sacrificial layer (20) is provided over the device element and a package cover layer (22) is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening (22) in the cover layer and the at least one opening (24) is sealed by an anneal process.

Abstract: A bus driver circuit for driving a bus voltage is provided. The bus driver circuit comprises: a bus line output (CANL) the bus voltage of which is driven by the bus driver circuit; a first transistor (M1) having a gate, the voltage at the gate of the first transistor (M1) determining the bus voltage at the bus line output (CANL); a first capacitor (C1) connected to the gate of the first transistor (M1) for driving the voltage at the gate of the first transistor (M1); a first switch (S1) connecting/disconnecting the first capacitor (C1) to a first voltage source (Vgm) via a first RC network comprising at least one resistor and at least one capacitor; and a second switch (S2) connecting/disconnecting the first capacitor (C1) to a predetermined fixed potential (GND 2) for discharging the first capacitor (C1) via a second RC network comprising at least one resistor and at least one capacitor. The first switch (S1) and the second switch (S2) are complementarily driven by a signal (TxD) on a data line.