Abstract: A digital phase locked loop (300) configured to receive a reference clock signal (302) and a channel control word (308), and to generate an output clock signal (304). The digital phase locked loop comprising an adjustable delay component (306) configured to: receive the reference clock signal (302), apply a time delay to the reference clock signal (302) in accordance with a time delay control signal (316); and provide a delayed reference clock signal (318).

Abstract: Various exemplary embodiments relate to a power factor corrector for low loads and a related method. The power factor corrector raises power factor at low loads or high mains voltages by having the a greater amount of current delivered to the load during the falling time of the absolute value of the mains AC voltage than during the applicable rising time. Various embodiments achieve this by increasing the switch-on time of a control switch during the falling time so that the majority of the switch-on time during a mains period occurs during the falling time. This may involve using a timing voltage increasing over a period within each half mains cycle to increase the switch-on time of conversion cycles in the falling time. This may also involve shifting the power conversion in time domain during each half mains cycle so that a majority of the time occurs during the falling time. Various embodiments may employ both methods.

Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.

Abstract: The invention relates to an electronic device for measuring and/or controlling a property of an analyte (100). The electronic device comprises: i) an electrode (Snsr) forming an interface with the analyte (100) in which the electrode (Snsr) is immersed in operational use, the interface having an interface temperature (T), and ii) a resistive heater (Htr) being thermally and capacitively coupled to the electrode (Snsr), the resistive heater (Htr) being configured for setting the interface temperature (T) by controlling a current through the resistive heater (Htr). The resistive heater (Htr) is provided with signal integrity protection for reducing the capacitive charging of the electrode (Snsr) by the resistive heater (Htr) if the current through the resistive heater (Htr) is modulated.

Abstract: A multi-stage demodulation circuit receives a given communication signal modulated by a superposition of at least a first modulation scheme and a second modulation scheme, the circuit having a first demodulation stage that demodulates the received communication signal according to the first demodulation scheme, and generates one or more bits representing the first modulation state of the signal. An intermediate demodulation circuit removes the first modulation from the received communication signal to generate an intermediate demodulation signal having only the second modulation. A second demodulation stage demodulates the intermediate demodulation signal according to the second demodulation scheme and generates one or more additional bits representing the second modulation state of the given communication signal.

Abstract: An apparatus (100) for feeding antenna elements of a phased array antenna, comprises: at least two transmission lines (101, 101) disposed in parallel and operated at a certain frequency as resonators, each of the transmission lines (101, 101) having a predetermined length dimensioned to be at least approximately an electrical quarter-wavelength of the operating frequency, a plurality of measuring positions provided on the transmission lines (101, 101) in spacings along the longitudinal direction (x) of the transmission lines, wherein each measuring position on one of the two transmission lines (101) faces directly a corresponding neighbored measuring position on the other transmission line (101) and such corresponding measuring positions being adjacent to each other in a direction transverse to the longitudinal direction of the transmission lines (101, 101) form a measuring position pair, respectively, wherein each of the circuits (110, 120, 130) detects and amplifies/attenuates the measuring signals from an

Abstract: A latency control mechanism for a communication system provides a known constant end-to-end delay between an audio source and one or more end node destinations, even in the case where different paths are used to reach the end nodes. A very low jitter time on the end-to-end latency is obtained, and the latency is controllable within a given range in dependence on the constraints imposed by the implementation. A block RX DPLL and latency control unit adjusts the reading moment and position from the RX buffer so that a delay between the time stamp taken at the source side by the transmitter time stamp unit, and the time stamp taken at the receiver side by receiver time stamp unit is constant and equal to a given value.

Abstract: An ear bud and noise reduction system actively reduce noise in one ear while the user listens with the other ear to an audio sound wave produced by the speaker of an electronic device (e.g., a cell phone or a wireless headset attachable to a single ear). The ear bud includes a microphone, an active noise reduction unit, and an audio speaker. The active noise reduction unit produces a noise reduction signal based on ambient noise sensed by the microphone in the vicinity of a first ear while an electronic device produces a first audio sound wave in the vicinity of a second ear. The audio speaker produces a second audio sound wave in the vicinity of the first ear based on the noise reduction signal to reduce or substantially cancel the ambient noise. The first and second audio sound waves may be produced independently of each other.

Abstract: A portable RFID device includes an analog modulation radio frequency transmitter and a data storage holding audio data files. In response to user entered commands the device retrieves the audio data files, applies digital to analog conversion to generate analog audio signals, and transmits the analog audio signals through the analog modulation RF amplifier. Optionally, the analog modulation RF amplifier is a frequency modulation (FM) modulator and transmitter, optionally using a UHF broadcast FM band. The transmitted analog modulated RF signal is received and played by a receiver and playback device proximal to the transmitter. Optionally, a locking operation is applied after storing the multimedia files, preventing subsequent altering of the files.

Abstract: A planar antenna device (AD) for a TV receiver (R) comprises i) a loop antenna (LA) comprising first (E1) and second (E2) ends spaced one from the other, ii) a tuning means (TM) connected to the first (E1) and second (E2) ends of the loop antenna (LA) and arranged to control the frequency of the VHF TV signals this loop antenna (LA) is able to receive from command signals, iii) a first ground plane (GP1) cooperating with the loop antenna (LA) in order to act as a UHF monopole in receiving TV signals with UHF frequencies, iv) a first coupling means (CM1) coupled to the loop antenna (LA) at a first chosen location and arranged to deliver the received VHF signals, v) a second coupling means (CM2) coupled to the loop antenna (LA) at a second chosen location and arranged to deliver the received UHF signals, vi) an amplification means (AM) coupled to the first ground plane (GP1) and arranged to amplify TV signals, and vii) a switching means (SM) arranged to couple the amplification means (AM) to the first coupling

Abstract: An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).

Abstract: Therefore, an electronic device is provided which comprises a plurality of processing units (IP1-IP6), and a network-based interconnect (N) coupling the processing units (IP1-IP6) for enabling at least one first communication path (C) between the processing units (IP1-IP6). The electronic device furthermore comprises at least one first monitoring unit (P1) for monitoring a data traffic of the at least one first communication path and for outputting monitoring results via at least one second communication path (MC1), and at least one second monitoring unit (P2) for monitoring a data traffic of the at least one second communication path (C) and for outputting monitoring results via at least one third communication path (MC2).

Abstract: The present invention relates to a converter circuit and a conversion method for converting an input signal of a first value to an output signal of a second value based on a switched operating mode, wherein an output feedback loop (40) and an additional input forward control loop (60) are provided. The additional input forward control loop (60) serves to correctly control a switching parameter not only with respect to the output load but also over a wide input voltage range. This leads to an improved power efficiency and reliability of the converter circuit.

Abstract: A transmitter has a power amplifier (40) to amplify an input signal having amplitude modulation, a supply voltage controller (10) to control a supply voltage of the power amplifier (40) according to the envelope, a sensor (R1) for sensing a modulation of a current drawn by the power amplifier (40), a delay detector (20) for detecting a delay of the controlled supply voltage relative to the sensed current, and a delay adjuster (30) for compensating the relative delay according to the detected delay. By sensing a current drawn, the delay detected can include any delay contributed by the power amplifier (40) up to that point, and yet avoid the more complex circuitry needed to derive the delay from an output of the power amplifier. Thus the distortion and out of band emissions caused by differential delays can be reduced more effectively.

Abstract: The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.

Abstract: In order to provide a switch device (100; 100?) connecting at least one first point (10, 12), in particular connecting at least one source device and/or at least another switch device, to at least one second point (20, 22, 24), in particular to at least one destination device and/or to at least another switch device, the switch device (100; 100?) comprising at least one virtual channel (30, 32), wherein it is possible to arbitrate and/or differentiate data, in particular data packets or data streams, being transmitted within the same virtual channel (30, 32), it is proposed that the switch device (100; 100?) comprises at least two ports (40, 42), in particular input ports, for receiving and/or at least two ports (50, 52), in particular output ports, for sending the data, in particular the data packet or data stream, the ports (40, 42, 50, 52) being respectively assigned to the virtual channel (30, 32).

Abstract: An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

Abstract: A frequency hopping receiver circuit has a frequency converter (12) and a hopping control circuit (14) coupled to the frequency converter (12), and configured to control frequency hopping of the received frequency, by controlling changes in frequency shift applied by the frequency converter (12). The frequency change is applied in combination with a temporary reduction in conversion gain of the frequency converter (12) during the change in frequency shift. The frequency converter may contain a mixer (122), a local oscillator circuit (120) and a controllable amplifier (124) coupled between the input of the frequency converter (12) and the mixer (122) or between the mixer (122) and the output of the frequency converter (12), or between the local oscillator circuit (120) and the local oscillator input of the mixer (122).

Abstract: A capacitor (110), wherein the capacitor (110) comprises a capacitor dielectric (112) comprising a dielectric matrix (114) of a first value of permittivity, and a plurality of nanoclusters (116) of a second value of permittivity which is larger than the first value of permittivity which are at least partially embedded in the dielectric matrix (114), wherein the plurality of nanoclusters (116) are formed in the dielectric matrix (114) by spontaneous nucleation.

Abstract: A method of and system for determining a number of pixels out of a plurality of pixels, which plurality of pixels forms an image strip, each pixel of the plurality of pixels having a specific colour component value is provided. The method involves determining a value of a first colour component of each pixel of the plurality of pixels, wherein the value corresponds to a first colour depth describable by a first number of bits, and binning the plurality of pixels into a second number of bins of a first histogram, wherein the second number is lower than a maximum value represented by the first number of bits, determining the number of entries in each bin of the first histogram and determining for each bin of the first histogram an average colour value of a second colour component of the pixels binned into the respective bin.