Abstract: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400).

Abstract: An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores.

Abstract: A control device is connected to at least one encryption/decryption device via at least one communication device. The control device is connected to a round key generator via at least one further communication device. The control device has at least one external key input, the at least one encryption/decryption device has at least one external data input and at least one external data output, and the at least one encryption/decryption device and the round key generator are decoupled from one another.

Abstract: A field-effect transistor having cells (18) each having a source region (22), source body region (26), drift region (20), drain body region (28) and drain region (24) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches (35) defining a gate region (31) adjacent the source or drain region (22, 24) and a longitudinally extending potential plate region (33) adjacent the drift region (20). Alternatively, a separate potential plate region (33) or a longitudinally extending semi-insulating field plate (50) may be provided adjacent the drift region (20). The transistor is suitable for bi-directional switching.

Abstract: The invention relates to a planar inductive component (11) comprising at least a first and a second concentric inductor, which include a first and a second spiral pattern (12A, 12B), respectively. Both spiral patterns have a first end point (13A, 13B) and a second end point (14A, 14B), are electrically interconnected, interlaced, and interrupted at the outer side, and provided with two contacts (16A, 16B) on one side of the opening (15A, 15B) and two contacts (17A, 17B) on the other side of the opening (15A, 15B). By interconnecting the first two contacts (16A, 16B) and the second two contacts (17A, 17B), respectively, both spiral patterns are connected in parallel. The spiral patterns (12A, 12B), which are magnetically coupled, have identical electrical and magnetic properties. This leads to a reduction of eddy current losses at high frequencies. This results in a planar inductive component (11) which is suitable for high-frequency operation with a high maximum quality factor Q.

Abstract: The invention relates to a sensor arrangement (1) comprising a magnet (2), a magnetic field sensor (3) and a twistable or rotatable rod (4), characterized in that the magnet (2) is arranged below the magnetic field sensor (3) and the twistable or rotatable rod (4) is arranged above the magnetic field sensor (3), wherein the rod (4) comprises a lower surface (6) generating a tilt angle between the surface and the plane of the magnetic field sensor.

Abstract: A commutating auto zero amplifier system, comprises a first amplifier (A1), a second amplifier (A2) and a switching arrangement which defines a two phase operation, with one amplifier in an output mode providing the output and the other amplifier in a zeroing mode during each phase. A capacitor arrangement (Cof1. Cot1) stores offset voltages, a buffer amplifier (B) couples the output from the amplifier in the output mode to an input of the amplifier in the zeroing mode. This eliminates voltage swings at the output of an amplifier as it switches between modes of operation.

Abstract: The present invention relates to a system-in-package that comprises an integration substrate with a thickness of less than 100 micrometer and a plurality of through-substrate vias, which have an aspect ratio larger than 5. A first chip is attached to the integration substrate and arranged between the integration substrate and a support, which is suitable for mechanically supporting the integration substrate during processing and handling. The system-in-package can be fabricated according to the invention without a through-substrate-hole etching step. The large aspect ratio implies reduced lateral extensions, which allow increasing the integration density and decreasing lead inductances.

Abstract: An electronic component (100) comprising a matrix (102) and a plurality of islands (103) embedded in the matrix (102) and comprising a material which is convertible between at least two states characterized by different electrical properties, wherein the plurality of islands (103) form a continuous path (104) in the matrix (102).

Abstract: The invention provides a method for fabricating a bipolar transistor applying a standard shallow trench isolation fabrication method to simultaneously form a vertical bipolar transistor (29) or a lateral bipolar transistor (49) in a first trench (5, 50) and a shallow trench isolation region (27, 270) in a second trench (7, 70). Further, the fabrication method may simultaneously form a vertical bipolar transistor (27) in the first trench (5, 50), a lateral bipolar transistor (49) in a third trench and a shallow trench isolation region (27, 270) in the second trench (7, 70).

Abstract: The invention relates to a method of communication between a communication station (1) and data carriers (2), and furthermore to such a communication station (1) and to such data carriers (2). According to the invention the communication station (1) is adapted to receive and identify response signals (RDB) of different lengths (L) supplied by the data carriers (2). Said length (L) of the response signals (RDB) provided by the data carriers (2), which data carriers (2) are adapted to generate response signals (2) with different lengths (L), is determined in or before an interrogation cycle (IPER) before the response signals (RDB) with said length (L) are supplied by the data carriers (2) in response to the interrogation signal (IDB). In a specific solution the length (L) is determined in each interrogation cycle.

Abstract: An electronic device is disclosed comprising a transceiver stage (140) for communicating signals between the electronic device and a further device; and a baseband processor arrangement (120) implementing a built-in self test arrangement for testing the transceiver channels of the electronic device (100). The built-in self test arrangement further comprises a plurality of records, each record comprising predetermined response deviations to different test signals caused by a parametric fault; and means for selecting those records from the plurality of records for which the predetermined response deviation corresponds to the deviation of the received response. The present invention is based on the realization that a deviation of a response to a test signal from an expected value is dependent on specific parametric faults in specific components in the test signal path and, in addition, on the shape of the test signal.

Abstract: Disclosed is an intermediate frequency processing device for processing both analogue and digital television intermediate frequency signals including vision and sound intermediate frequency signal components, comprising an intermediate frequency signal input for receiving digital or analogue intermediate frequency signals, a processing section, coupled to said intermediate frequency signal input means, for processing intermediate frequency signals, and an output for outputting signals processed in said processing section. The processing section comprises a first band pass filter (1,2,3) connected to said intermediate frequency signal input, and at least two parallel processing portions (4,6a,7,19-22,30-40,42-45;5,6b,8,18,23-29,46) coupled in parallel to said band pass filter (1,2,3), wherein each of said processing portions includes an inphase quadrature processing means (18,23;19,22).

Abstract: The present invention discloses a wireless telephone system using microphone arrays together with additional signal processing to suppress the background noise in the surrounding environment. The signal processing resources of a wireless telephone and multi-channel transmission capabilities of the Bluetooth transmission are used to suppress the background noise. The wireless telephone system includes a Bluetooth transceiver communicating to a wireless telephone through a multi-channel Bluetooth transmission, and an array of microphones coupled to the Bluetooth transceiver. The array of microphones includes a first microphone producing a first audio signal output and a second microphone producing a second audio signal output. The first audio signal output and second audio signal output are transmitted to the wireless telephone through the first channel and second channel of multi-channel Bluetooth transmission respectively.

Abstract: The invention relates to a circuit arrangement (30, 40, 70, 80, 90) of a low-noise linear input amplifier comprising a parallel circuit of a common-base circuit (20) and a common-emitter circuit (30), the emitters of two first transistors (Q3, Q4) are interlinked and the bases of two second transistors (Q1, Q2) are intercoupled, the collectors are interconnected in parallel with the output, and the source voltage (VG) is interlinked with the emitters of the second transistors (Q1, Q2) and with the bases of the first transistors (Q3, Q4), in which a linearization of the output current (OUTLNA1,2) as a function of the source voltage (VG) is achieved by a linearization of the transfer function, such as the tangential hyperbolic function, of the first and second transistors (Q1, Q2, Q3, Q4).

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D) to be stored on the non-volatile memory device; a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from; and—an encryption circuit (50) for encrypting the external data (D) forming encrypted data (D?, D?) using unique data (K, K1, K2) from at least the first non-volatile memory block (100) as an encryption key, the encrypted data (D?, D?) at least being stored into the second non-volatile memory block (200).

Abstract: Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.

Abstract: A digital camera includes an image sensor; a buffer memory adapted to receive images from the image sensor and to store the images therein; an image processor adapted to receive selected images and to process the selected images, including applying a video compression algorithm to the selected images; an image storage device adapted to store the processed, selected images; and an image selector adapted to select the selected images among the stored images in the buffer memory based on at least one image selection criterion, and to cause unselected stored images to be discarded from the buffer memory.

Abstract: A device (100) for processing data, the device (100) comprising an integrator unit (103, 104) adapted for integrating an input signal (V1) and a correction unit (101, 102) adapted for correcting a clipping integrator unit (103, 104) by forcing a zero-crossing of an output signal (V1, V2) of the integrator unit (103, 104).

Abstract: The present invention discloses a method and a system for activating a communication device in presence of a field generated by a near field communication (NFC) tag reader in a near field communication (NFC) environment. The presence of a field generated by a NFC tag reader is automatically detected using detection circuits. Once the field is detected, the presence of the field is signaled to the communication devices associated with the NFC environment. The communication devices are then switched automatically to an appropriate mode according to the field. The method and system of the present invention removes the additional user interaction in pairing various communication devices in the NFC environment.