Abstract: The invention relates to a cluster coupler in a time triggered network for connecting clusters operating on the same protocol. Further, it relates to a triggered network having a plurality of clusters, which are coupled via the cluster coupler. It also relates to a method for communicating between different clusters.

Abstract: There is a method of manufacturing a semiconductor device with a dual gate field effect transistor, the method including a semiconductor body a semiconductor material having a surface with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type opposite to the first conductivity type between the source region and the drain region and with a first gate region separated from the surface of the semiconductor body by a first gate dielectric above the channel region and with a second gate region situated opposite to the first gate region and formed within a recess in an opposite surface of the semiconductor body so as to be separated from the channel region by a second gate dielectric wherein the recess is formed with a local change of the doping of the channel region and by etching starting from the opposite surface of the semiconductor body.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (1) comprising a high-ohmic semiconductor substrate (2) which is covered with a dielectric layer (3) containing charges, on which dielectric layer one or more passive electronic components (4) comprising conductor tracks (4) are present, and at the location of the passive elements (4) a semiconductor region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), a first conductivity-type conducting channel induced in the semiconductor substrate (2) by the charges being interrupted by, and at the location of, the semiconductor region (5). According to the invention, the semiconductor region (5) is monocrystalline and of a second conductivity type, opposite to the first conductivity type. In this way the charge of an induced channel is locally compensated by the charge of the semiconductor regions (5).

Abstract: The invention relates to a method of fabricating a CMOS device, comprising providing a semiconductor substrate (101) having therein a layer of insulating material (102), the method comprising providing a layer (106) of a first material over the insulating layer (102), the thickness of the layer (106) of the first material being less in a first region (103) for supporting a first active device than in a second region (104) for supporting a second active device. A layer (107) of a second material is then deposited over the layer (106) of a first material, and the structure is then subjected to a thermal treatment to alloy the first and second materials. The portion of the layers over the first region is entirely alloyed, whereas the portion of the layers over the second region is not, so that a portion (109) of the layer (106) of the first material remains.

Abstract: An interface device (D) is dedicated to debugging and/or tracing in a computer system (CS) comprising at least one master (M1, M2, M3) working with at least one slave (SLj) adapted to be readable and writable at chosen addresses, each master being adapted to execute tasks and to deliver slave addresses for reading and/or writing purposes. This interface device (D) comprises i) a group of first FIFO memories (SMi) each assigned to one master for storing data representative of the tasks it executes, ii) a group of dynamically allocatable second FIFO memories (DFk) linkable to one another and to the first FIFO memories (SFi), and iii) processing means (PM) arranged to compute dynamically the FIFO memory size required by each master at a given time, considering the tasks it is executing, and to allocate dynamically a number of second FIFO memories (DFk) to each master chosen according to the corresponding computed FIFO memory size.

Abstract: An electronic device with a CMOS circuit (CC) comprises a first driver circuit (10) having a first and second PMOS transistor (P1, P2) and a first and second NMOS transistor (N1, N2). The electronic device furthermore comprise a second driver circuit (20) with a third and fourth PMOS transistor (P3, P4) and a third and fourth NMOS transistor (N3, N4). The second driver circuit (20) is complementary to the first driver circuit (10) and switches in the opposite direction to the first driver circuit (10). A gate of the second and fourth PMOS transistor (P2, P4) is coupled to a first bias voltage (REPp) and a gate of the second and fourth NMOS transistor (N2, N4) is coupled to a second bias voltage (REFn). A first capacitance (C3) is coupled between the gate and the drain of the fourth PMOS transistor (P4) and a second capacitance (C4) is coupled between the gate and the drain source of the fourth NMOS transistor (N4).

Abstract: A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.

Abstract: An asymmetric semiconductor device (3) that includes an integrated high voltage diode (72), including: a substrate comprising an epitaxial layer (47) and a deep well implant (42) of a first type patterned above the epitaxial layer; a shallow trench isolation (STI) region (46) separating a cathode from an anode; a first well implant (40) of a second type residing below the anode; and a deep implant mask (34) of the second type patterned above the deep well implant and below both the cathode and a portion of the STI region.

Abstract: There is provided a method and apparatus for maintaining a bias current (IBIAS1) that flows through two transistors (MN2, MP2) at a target level. The two transistors are both connected to form a series network between positive (VDD) and negative (GND) voltage supply terminals. The bias current flows through the two transistors (MN2, MP2) when the circuit is at equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage (VB1, VB2) that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit (25) that measures a circuit parameter (VDD) that is indicative of the level of bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors (VB1, VB2) SO as to alter the transistors threshold voltages and maintain the level of bias current at a target level.

Abstract: A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately.

Abstract: Therefore, an electronic device is provided which comprises a plurality of processing units (IP1-IP6), and a network-based interconnect (N) coupling the processing units (IP1-IP6) for enabling at least one first communication path (C) between the processing units (IP1-IP6). The electronic device furthermore comprises at least one first monitoring unit (P1) for monitoring a data traffic of the at least one first communication path and for outputting monitoring results via at least one second communication path (MCI), and at least one second monitoring unit (P2) for monitoring a data traffic of the at least one second communication path (C) and for outputting monitoring results via at least one third communication path (MC2).

Abstract: An IC (100) for communicating over a data communication bus (220) comprising a first pair of conductors including a data signal conductor (SDA) and a synchronization signal conductor (SCL), e.g. an I2C bus, is disclosed. The IC comprises a group of address pins (106a-c) for defining the bus address of the integrated circuit (100), each address pin being arranged to be coupled to a conductor from a group of conductors comprising the first pair of conductors and a second pair of conductors including a conductor for carrying a fixed high potential (Vdd) and a conductor for carrying an fixed low potential (GND).

Abstract: The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).

Abstract: A damascene process is described using a copper fill process to fill a trench (12). The copper fill (20) is started with a deposited seed layer which includes (5) copper and titanium. Some titanium migrates to the surface during the copper fill process. The structure is annealed in a nitrogen atmosphere which creates a self-aligned TiN barrier (24) at the surface of the copper fill (20). Air gaps (26) may be created in the same annealing process. The process may be used to form a multilayer structure.

Abstract: The present invention relates to MEMS device that comprises a first electrode, and a second electrode suspended with a distance to the first electrode with the aid of a suspension structure. The MEMS device further comprises at least one deformation electrode. The second electrode or the suspension structure or both are plastically deformable upon application of an electrostatic deformation force via the deformation electrode. This way, variations in the off-state position of the second electrode that occur during fabrication of different devices or during operation of a single device can be eliminated.

Abstract: An R.F. transmitter circuit has an amplifier (30), a matching network (40) coupled to an output of the amplifier, a programmable resistance (35) coupled to the output of the amplifier, and a controller (60) arranged to control the programmable resistance, and to determine a matched output impedance of the amplifier by detecting a change in the amplifier output for different values of the programmable resistance. This output impedance can be used to adjust the matching to achieve optimum gain or optimum efficiency or other characteristic, during manufacture, test, or in use.

Abstract: In a method of processing data, an RFID signal (6) sent by a reader (3,5) via a field generated by the reader (3,5) is received at a passive RFID transponder (2). The transponder (2) comprises a dedicated receiver (28) for receiving a time signal (8), which is wirelessly sent By an external sender (4) and comprises information about the present time. The transponder (2) including the dedicated receiver (28) is powered utilizing the field such that the dedicated receiver (28) detects the time signal (8) and decodes the present time. Utilizing the transponder (2), the first data (7) contained in the RFID signal (6) is decoded and processed. Second data (9) which are time stamped by said transponder (2) utilizing said present time are generated, and a response signal (10) comprising the second data (9) is transmitted from the transponder.

Abstract: The present invention relates to a protection circuit and method of protecting a semiconductor circuit against a temporary excessive voltage on a supply line, wherein a first trigger signal is generated in response to a detection of an excessive voltage on the supply line and a clamp element (M1) is activated by applying a boosted second trigger signal at a voltage higher than the first trigger signal to a control terminal of the clamp element (M1) in response to said first trigger signal, to thereby generate a low resistive path between said supply line and a lower reference potential. Thereby, the clamp element (M1) is activated with a higher voltage and can thus be made smaller in width. Because the clamp element is smaller, a remote trigger circuit can be sized tighter and faster.

Abstract: A method of manufacturing an inductor embedded into a semiconductor chip package (100) is described, which method comprises providing a carrier (102; 202; 302) having, between a first side and an opposite second side, a first conductive layer (104; 503), an intermediate layer (205; 505), a second conductive layer (106; 504), forming an inductor and contact pads for the chip by patterning the first conductive layer (104; 503) from the first side of the carrier (102; 202; 302), assembling the chip and providing an encapsulation (514) and forming terminals of the package, by patterning the second conductive layer (106; 504) from the second side of the carrier.

Abstract: The present invention shows a Doherty type of amplifier arrangement comprising a plurality of parallel unit cells. Each unit cell is of relatively low power. Suitably it comprises a compensation circuit at the input of the main amplifier and peak amplifier stage.