Patents Assigned to NXP
  • Publication number: 20100044865
    Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.
    Type: Application
    Filed: November 27, 2007
    Publication date: February 25, 2010
    Applicant: NXP B.V.
    Inventors: Joaquin Torres, Laurent Gosset, Vincent Arnal, Sonarith Chhun
  • Publication number: 20100045247
    Abstract: A power supply system comprises a parallel arrangement of a linear amplifier (LA) and a DC-DC converter (CO). The linear amplifier (LA) has an amplifier output to supply a first current (II) to the load (LO). The DC-DC converter (CO) comprises: a converter output for supplying a second current (12) to the load (LO), a first inductor (L1), and a switch (SC) coupled to the first inductor (L1) for generating a current in the first inductor (L1), and a low-pass filter (FI) arranged between the first inductor (L1) and the load (LO). The low pass filter (FI) comprises a first capacitor (C1; CA) which has a first terminal coupled to the switch (SC) an a second terminal coupled to a reference voltage level (GND), and a second inductor (L2; LC) which has a first terminal coupled to the first inductor (L1) and a second terminal coupled to the load (LO).
    Type: Application
    Filed: April 12, 2006
    Publication date: February 25, 2010
    Applicant: NXP B.V.
    Inventors: Pieter G. Blanken, Paul Anthony Moore, Derk Reefman, Brian Minnis
  • Publication number: 20100046773
    Abstract: An acoustic device (200, 300) comprising an oscillatory compound membrane (201) comprising a plurality of layers (202, 203, 205), wherein one of the plurality of layers (202, 203, 205) is a thermoplastic layer (203, 205), wherein the thermoplastic layer (203, 205) is joined to at least one further component (204, 206, 207) of the acoustic device (200).
    Type: Application
    Filed: October 16, 2007
    Publication date: February 25, 2010
    Applicant: NXP, B.V.
    Inventors: Susanne Windischberger, Ewald Frasl
  • Publication number: 20100045356
    Abstract: A device (100) for processing data, the device (100) comprising an integrator unit (103, 104) adapted for integrating an input signal (V1) and a correction unit (101, 102) adapted for correcting a clipping integrator unit (103, 104) by forcing a zero-crossing of an output signal (V1, V2) of the integrator unit (103, 104).
    Type: Application
    Filed: March 11, 2008
    Publication date: February 25, 2010
    Applicant: NXP, B.V.
    Inventors: Marco Berkhout, Benno Krabbenborg
  • Patent number: 7667370
    Abstract: A generating device (1) for generating a useful stream of a medium (2) comprises at least a medium stream source (14) for generating a high-frequency medium stream (15) and at least a medium stream diode (36, 37) for cooperating with the generated medium stream (15), and at least one medium stream sink (40, 41) for cooperating with the medium stream influenced by the medium stream diodes (36, 37), wherein the at least one medium stream sink (40, 41) suppresses high-frequency stream components in the medium stream such that a useful medium stream (2) in a low-frequency range is obtained.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: February 23, 2010
    Assignee: NXP B.V.
    Inventor: Josef Lutz
  • Publication number: 20100041186
    Abstract: A method of manufacturing an I-MOS device includes forming a semiconductor layer (2) on a buried insulating layer (4). A gate structure (23) including a gate stack (14) is formed on the semiconductor layer, and used to (5) self align the formation of a source region (28) by implantation. Then, an etch step is used to selectively etch the gate structure (23) and this is followed by forming a drain region (36) by implantation. The method can precisely control the i-region length (38) between source region (28) and gate stack (14).
    Type: Application
    Filed: December 12, 2007
    Publication date: February 18, 2010
    Applicant: NXP, B.V.
    Inventor: Radu Surdeanu
  • Publication number: 20100042899
    Abstract: A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.
    Type: Application
    Filed: September 10, 2007
    Publication date: February 18, 2010
    Applicant: NXP, B.V.
    Inventors: Tianyan Pu, Sergi V. Sawitzki
  • Publication number: 20100040246
    Abstract: A compound membrane (100) for an acoustic device (200), the compound membrane (100) comprising a first layer (101) and a second layer (102), wherein a value of Young's modulus of the second layer (102) does not vary more than essentially 30% in a temperature range between essentially ?20° C. and essentially +85° C.
    Type: Application
    Filed: October 6, 2007
    Publication date: February 18, 2010
    Applicant: NXP, B.V.
    Inventors: Susanne Windischberger, Josef Lutz, Ewald Frasl
  • Publication number: 20100039000
    Abstract: A bulk acoustic wave, BAW, resonator device comprising first and second metal layers (10, 20) and an intervening piezoelectric layer (30), the first metal layer (10) comprising spaced first and second portions (12, 14), wherein the first and second portions (12, 14) are each arranged as a plurality of interconnected fingers (16, 18), and wherein each of the plurality of fingers (16) of the first portion (12) is acoustically coupled to at least one of the fingers (18) of the second portion (14). In one embodiment the fingers of the first portion (12) are interlaced with the fingers (18) of the second portion (14), thereby providing direct coupling. In another embodiment the acoustic coupling between the fingers of the first and second portions is provided indirectly by further portions (15) of the first metal layer (10).
    Type: Application
    Filed: May 23, 2006
    Publication date: February 18, 2010
    Applicant: NXP B.V.
    Inventors: Robert F. Milson, Frederik W., M. Vanhelmont, Andreas B., M. Jansman, Jaap Ruigrok, Hans-Peter Loebl
  • Publication number: 20100038972
    Abstract: The invention relates to a voltage-boosting stage (100) comprising a first capacitive voltage circuit (S1, S2, S3, S4, CO, Cb) coupled to a power supply (Vs) and providing an output voltage at an output terminal. The voltage-boosting stage further comprises a second capacitive voltage circuit (S5, S6, S7, S8, C1, Cb) coupled to a power supply (Vs) and providing another output voltage at another output terminal the output terminal and the other terminals being coupled together and further coupled to a supply terminal of a power stage (S9, S1O) for implementing a two-level boosted power stage.
    Type: Application
    Filed: October 19, 2007
    Publication date: February 18, 2010
    Applicant: NXP, B.V.
    Inventors: Berry A. J. Buter, Alexandre Huffenus
  • Publication number: 20100039184
    Abstract: An electronic device (ED) is intended for generating a local oscillator signal having a chosen frequency FLO from a main signal outputted by a voltage-controlled oscillator (VCO) and having a fundamental frequency FVCO and harmonics thereof. This electronic device (ED) comprises a frequency division means (D1, D2) arranged to divide the frequency of a signal by a chosen factor N and a filter means (F1, F2) arranged to select a chosen Mth order harmonic of a signal, these frequency division means (D1,D2;D) and filter means (F1, F2) being arranged to process the main signal in common to output the local oscillator signal with a chosen frequency FLO equal to M×FVCO/N.
    Type: Application
    Filed: March 1, 2006
    Publication date: February 18, 2010
    Applicants: NXP B.V.
    Inventors: Dominique Delbecq, Michel Germe
  • Publication number: 20100041189
    Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.
    Type: Application
    Filed: September 15, 2009
    Publication date: February 18, 2010
    Applicants: STMicroelectronics (Crolles) 2 SAS, STMicroelectronics S.A., NXP B.V.
    Inventors: Markus Müller, Alexandre Mondot, Pascal Besson
  • Publication number: 20100042862
    Abstract: There is provided a system for reducing the risk of data corruption occurring in wireless systems, by reducing the risk of an un-expected disconnection occurring between a client device (20; 52, 54, 56) and a host device (20; 50). The client device monitors its own power supply, and when the client device determines that its power supply capacity is almost exhausted, the client device sends a low power notification (5; 55) to the host device. The host device receives the low power notification, and in response closes the wireless connection to the client device, thereby preventing an unexpected disconnection from occurring when the clients power supply is finally exhausted.
    Type: Application
    Filed: January 4, 2008
    Publication date: February 18, 2010
    Applicant: NXP, B.V.
    Inventors: Yuxi Sun, Bart Vertenten
  • Publication number: 20100042740
    Abstract: A method and a device is presented for communicating a first data stream encoded according to a non-PCM format through a communication link that is designed communicating a data stream encoded according to a PCM format. The method and device receive a first data stream encoded according to a non-PCM format. The received data stream comprises a plurality of data-packets. The method and device pack the first data stream into a second data stream. The second data stream has plurality of data-packets. Each of the data-packets of the second data stream includes a discontinuity according to the PCM format. The second data stream is communicated through the link. A method and a device are further provided for receiving the second data stream via the link and for identifying the format of the received data stream by examining for the discontinuity.
    Type: Application
    Filed: June 15, 2007
    Publication date: February 18, 2010
    Applicant: NXP B.V.
    Inventor: Puranjoy Bhattacharya
  • Patent number: 7663567
    Abstract: An antenna structure (106) comprising a first electrically conductive element (102) having a first end and a second end, a second electrically conductive element (103) having a first end and a second end, and a coupling structure (104) short-circuiting the first electrically conductive element (102) with the second electrically conductive element (103) by means of electrically connecting the electrically conductive elements (102, 103) at positions between the first and the second ends, wherein an integrated circuit (105) is connectable between the first end of the first electrically conductive element (102) and the first end of the second electrically conductive element (103).
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: February 16, 2010
    Assignee: NXP B.V.
    Inventor: Achim Hilgers
  • Patent number: 7664998
    Abstract: A modification of a predetermined, memory-size-dependant number of nonvolatile memory cells turns them into ROM cells with a fixed content pattern. Since these additional ROM cells do not require much effort during manufacturing and use only small additional space on the memory chip or the integrated circuit, but provide significant advantage for testing. When using pairs of essentially symmetrical non-volatile memory cells, each pair having a common bit line, the removal or interruption of this bitline contact may serve to impress a fixed value, e.g. a ‘0’, into this pair and vice versa. During test, a simple and therefore only minimal time requiring pattern, preferably a checkerboard pattern, is written into and read from the non-volatile memory, allowing a quick determination of the decoders' correct function.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: February 16, 2010
    Assignee: NXP B.V.
    Inventors: Steffen Gappisch, Georg Farkas
  • Patent number: 7663917
    Abstract: A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells (14, 16) are programmed with opposite data to increase the robustness of the retrieval process, and they are cross-coupled to the internal nodes (A, B) of the static memory cell, one the non-volatile cells (14) having a control gate connected to B and its source to A, and the other non-volatile element (16) having a control gate connected to A and its source to B. The drain of each non-volatile element (14, 16) is connected by means of a respective pMOS transistor (18, 20) to a program supply means.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 16, 2010
    Assignee: NXP B.V.
    Inventors: Roger Cuppens, Anthonie Meindert Herman Ditewig
  • Publication number: 20100034302
    Abstract: A method of synchronizing multi-carrier systems is provided, wherein the method comprises inserting a predefined frequency domain signal into a signal on a transmitter side of a multi-carrier system and multi-carrier modulating the signal. Furthermore, the method comprises transmitting the multi-carrier modulated signal via a carrier channel to a receiving side of the multi-carrier system, and synchronizing the multi-carrier modulated signal by using the predefined frequency domain signal portion of the multi-carrier modulated signal.
    Type: Application
    Filed: February 7, 2008
    Publication date: February 11, 2010
    Applicant: NXP, B.V.
    Inventors: Alessio Filippi, Semih Serbetli, Ying Wang
  • Publication number: 20100032848
    Abstract: It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first isolator layer (5) contacting the surface (17) of the substrate in a first region (a); a first metal layer (9) contacting the surface (17) of the substrate (3) in a second region (b) adjacent the first region (a) and partly overlapping the first isolator layer (5); a second isolator layer (11) at least partly overlapping the first isolator layer (5) and the first metal layer (9); a second metal layer (13) at least partly overlapping the second isolator layer (11) in the second region (b); wherein a maximum thickness (U) of the second metal layer (13) perpendicular to the surface (17) of the substrate (3) is smaller than a maximum thickness (t0) of the first isolator layer (5) perpendicular to the surface (17) of the substrate (3).
    Type: Application
    Filed: November 12, 2007
    Publication date: February 11, 2010
    Applicant: NXP, B.V.
    Inventors: Bengt Philippsen, Hans-Joerg Klammer
  • Publication number: 20100033175
    Abstract: A high-performance, integrated AMR sensor has compensation and flipping coils for signal conditioning of the sensor output. At least one of the coils is formed in the laminate that connects the AMR sensor with its IC within a single package. As a result, the dimensions of the die area of the AMR sensor and the package size can be kept small.
    Type: Application
    Filed: March 11, 2008
    Publication date: February 11, 2010
    Applicant: NXP, B.V.
    Inventors: Hans Boeve, Stephan Jansen, Teunis Jan Ikkink, Harris Duric