Abstract: Methods are provided for effecting functional control of program flow and/or data flow in digital signal processors and in processors which have closed and separated modules for effecting the program and data flow control or which operate in parallel arithmetic-logic units. The methods enhance the functionality of the signal processor to such an extent that the units of the processor, without time delays, are adapted, with regard to their energy consumption, to the latest demands of signal processing. The methods provide additional possibilities for saving energy which are enabled by algorithm-related shutdown of functional units. An external hardware-related signal input into the processor or a software-related state output from the program flow in the processor may be used to trigger an interruption in the clock pulse supply for the respective functional units for the period of time during which these functional units are not used.

Abstract: A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region (22) doped to have the second conductivity type above a drain region (20) doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region (4) and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.

Abstract: A road toll system comprises a vehicle-mounted unit comprising a satellite navigation receiver implementing a position tracking function, a memory device storing toll payment information and means for determining the routes taken by the vehicle based on the position tracking information. A disabling system is provided for disabling the vehicle operation based on the toll payment information. This system uses a satellite navigation receiver to enable infrastructure-free road tolling to be implemented. The system includes a function disabling the vehicle if the road toll fees have not been paid. This saves effort in tracking down users that do not pay their tolls.

Abstract: A method (100) is disclosed of generating an identifier from a semiconductor device (600) comprising a volatile memory (610) having a plurality of memory cells. The method comprises causing (110) the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving (120) the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method (100) is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM.

Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (12) and a silicon semiconductor body (11) and comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type, and a collector region (3) of the first conductivity type, on the surface of the semiconductor body (11) in which the collector region (3) is formed at least an epitaxial semiconductor layer (20,21,22) being deposited in which the base region (2) is formed, on top of this an etch stop layer (15) being deposited on which a silicon low-crystalline semiconductor layer (24) is deposited in which a connection zone of the base region (2) is formed and in which at the location of an emitter region (1) to be formed an opening (7) is provided running up to the etch stop layer (15), a portion of the etch stop layer (15) covering the opening (7) being removed by means of etching and also an adjoinin

Abstract: The invention related to a turbo decoder comprising SISO decoding modules each other interconnected in a feedback control scheme having scaling modules for applying a scaling factor to extrinsic information delivered by said SISO decoding modules. The turbo decoder comprises a selection module for adaptively selecting said scaling factor based on a number of decoding iterations of the turbo decoder.

Abstract: A method and apparatus for generating gamma corrected analogue voltages uses a first ladder resistor arrangement (34) to provides a first set of analogue voltage levels. A second set of voltages (x) is selected by programming a multiplexer arrangement (36) at the output of the first ladder resistor arrangement (34). A second ladder resistor arrangement (32) is used to provide a third set of analogue voltage levels which are at intermediate voltage levels between voltage levels of the second set (x). The output (g) is the buffered voltages of the second and third sets. This arrangement enables the amount of data that needs to be programmed to be reduced to a minimum required to implement the desired differences between the gamma functions. The voltages in the second set do not need to be evenly spaced, and more variability in the shape of the gamma curve can be provided where it is needed to best reflect different characteristics of possible displays to be driven.

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: A vehicle data recorder comprises a front end RF receiver and a memory device for storing sampled satellite positioning signal data from the 5 front end receiver. The memory device stores a block of sampled data corresponding to a time period leading up to the time of an incident involving the vehicle. The data can be stored with a low cost system, and can be analysed after the incident by a remote data processing station.

Abstract: According to an exemplary embodiment a random number generator system, comprises a pre-processing unit, and a random number generation unit, wherein the pre-processing unit is adapted to calculate an internal seed out of an external seed and/or system variables and/or dynamic variables related to stack, and wherein the random number generation unit is adapted to generate a random number by using a determined function, wherein the determined function is a function of the internal seed and of at least one dynamic runtime variable related to the stack.

Abstract: A data processing system comprises a Flash memory (120) having a storage space partitioned in a plurality of storage pages (P?). Each storage page comprises a memory reliability indicator indicative for the reliability of a storage region of the memory. Coupled to the Flash memory is a controller (150) for the Flash memory, that includes a facility for protecting data against errors occurring during storage in the Flash memory and for detecting and/or correcting errors in the data stored in the data, when retrieved from the Flash memory. A data processing unit (100) is coupled to the controller (150) that has access to a working page (P) comprising a first section of user data and a second section of management information, including a memory reliability indicator. The data processing system is characterized by a data re-arranging facility (105) for subdividing the data in the work page into a plurality of portions.

Abstract: The invention relates to operating an Integrated Circuit (IC). The present inventor has assessed that IC systems may suffer from limited lifetime e.g. due to overheating. Among others the invention discloses a method of operating an IC (304), the method comprising inputting power to the IC in bursts (102, 108, 116), sensing (118) an IC temperature using a temperature sensor (306), operating the IC by controlling the power (316) to be outputted by the IC during a burst (108, 116) in dependence of the sensed IC temperature compared to a reference IC temperature (318) using a controller (202), wherein the IC temperature is obtained at a predetermined moment prior to a start (612) of a burst (108, 616), and the IC is operated by setting (120) an allowable power (106) to be outputted by the IC prior to the start of said burst (108).

Abstract: The invention relates to a time triggered network used in particular in an automotive network having a plurality of clusters. Each cluster (A-X) includes a plurality of nodes (11).

Abstract: The present invention relates to a counter circuit and method of controlling such a counter circuit, wherein a first counting section counts in accordance with a state-cycle, and a second counting section is clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the at least one invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.

Abstract: The electronic slave device (6) comprises a hardware data packing block having: • a configurable multiplexing unit (44) having inputs connected to system bus (8) wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory (18) for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; • a format register (40), the value of which can be set by an external master device (4) to at least two different values; and • a logic circuit (48) capable of setting the connections of the multiplexing unit (44) according to the value of the format register (40) to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.

Abstract: A method of manufacturing a FET gate with a plurality of materials includes depositing a dummy region 8, and then forming a plurality of metallic layers 16, 18, 20 on gate dielectric 6 by conformally depositing a layer of each metallic layer and the anisotropically etching back to leave the metallic layer on the sides 10 of the dummy region. The dummy region is then removed leaving the metallic layers 16,18, 20 as the gate over the gate dielectric 6.

Abstract: The invention describes a power amplifier comprising a first transistor (MHS) having a first control terminal and a first main current path coupled between a first supply terminal (Vdd) and a first node (VH), a second transistor (MLS) having a second control terminal and a second main current path coupled between a second supply terminal (Vss) and a second node (VL), a first controlled resistor (MHC) coupled between the first node and an output node (Vout) of the amplifier, a second controlled resistor (MLC) coupled between the second node and the output node (Vout) of the amplifier, the first transistor being controlled by a first driver comprising a level shifting circuit, and the second transistor being controlled by a second driver including a time delaying circuit.

Abstract: In order to provide a security system, in particular in a motor vehicle (10), comprising a transmitter which transmits a signal in the form of an electromagnetic field (11, 14) and a transportable receiver (12) which receives the signal and sends back a corresponding response signal to a further receiver, in which it is more difficult to imitate the signal transmitted by the transmitter, it is proposed that a gradient of the electromagnetic field (11, 14) can be detected by the receiver (12).

Abstract: In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.