Abstract: A wireless media arrangement streams media over a local packet-based wireless network. According to an example embodiment, such a wireless media arrangement (e.g., 100) includes a digitally-encoded non-volatile storage device (NSD) (e.g., 110) such as a hard disc drive (HDD) that stores media, reloadable memory (e.g., 115) such as random-access memory (RAM), a media center (e.g. 105) to stream the stored media to a media playback device over the local network, and an embedded media server (e.g., 120). The media server wirelessly discovers and communicates with a media playback device (e.g., 125) on a local network. The media server also stores database tables on the NSD identifying the stored media. Upon startup, the media server loads a current version of the database tables into the reloadable memory; however, if an error is detected in the current version, then a pervious version of the database tables is loaded.

Abstract: A biosensor chip (100) for detecting biological particles, the biosensor chip (100) comprising a sensor active region (101) being sensitive for the biological particles and being arranged in a Back End of the Line portion (102) of the biosensor chip (100).

Abstract: A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).

Abstract: The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M1) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M1) in a circuit having a very thin gate oxide, which is in particular produced by a deep sub micron process a circuit arrangement is proposed for controlling a high side CMOS transistor (M1) in a high voltage deep sub micron process, wherein the high side CMOS transistor (M1) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M1) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference (11) having a capacitor (C1), which is charged for switching on and discharged for switching off the high side CMOS transistor (M1).

Abstract: A method of acquiring a received spread spectrum signal comprises receiving a spread spectrum signal, analysing the received signal to detect interference within the received signal, and adapting the baseband processing of the received signal to reduce power consumption during periods of detected interference. This allows the GPS processing resources to be focussed on areas of signal where there is little or no interference, and this is possible without modification to the source of interference. The interference is detected from an analysis of the received signal, and in particular before the baseband digital signal processing.

Abstract: A magnetic field sensor circuit comprises a first magneto-resistive sensor (Rx) which senses a first magnetic field component in a first direction to supply a first sense signal (Vx). A first flipping coil (FC1) applies a first flipping magnetic field with a periodically changing polarity to the first magneto-resistive sensor (Rx) to cause the first sense signal (Vx) to have alternating different levels synchronized with the first flipping magnetic field. A second magneto -resistive sensor (Ry) senses a second magnetic field component in a second direction different than the first direction to supply a second sense signal (Vy). A second flipping coil (FC2) applies a second flipping magnetic field with a periodically changing polarity to the second magneto -resistive sensor (Ry) to cause the second sense signal (Vy) to have an alternating different levels synchronized with the second flipping magnetic field. The first flipping magnetic field and the second flipping magnetic field have a phase shift.

Abstract: The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424) between a first and a second metal structure.

Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire (135) located in an interconnect layer of said semiconductor device, the at least one wire (135) having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire (135?) is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.

Abstract: Method for exchanging data between an NFC device (10) and a transceiver device (20) via a single communication channel (30), comprising the steps:—extracting a clock for the data exchange on the communication channel (30) from an external RF field (50); and—coding of the data via symbols, wherein the symbols comprise status information relating to simultaneous accesses of contactless card functionalities (21, 22, 23) on the transceiver (20) to the single communication channel (30).

Abstract: The package comprises a chip and a plurality of frame contact pads. The chip is attached to the frame contact pads in a die attach area with a die attach adhesive. The chips is coupled to frame contact pads outside the die attach area with connecting elements. The chip, the connecting elements and the frame contact pads outside the die attach area are anchored in an electrically insulating encapsulation. The frame contact pads each comprise a first patterned layer and a second patterned layer, which second layer has the surface that is exposed outside the encapsulation. At least a portion of the frame contact first patterned layer with a first pattern that comprises at least one flange/lead that is outside the second patterned layer when seen in perpendicular projection of the first layer on the second layer.

Abstract: Method for manufacturing a crossbar circuit on a substrate (1), the crossbar circuit comprising a first grid of first wires (10) and a second grid of second wires (17), the first wires extending in a first direction, the second wires extending in a second direction, the first direction and the second direction being arranged relative to each other to form a single two-dimensional wire grid, each first wire being separated from each second wire by an intermediate layer (14) located at a location where the first and second wires overlap; the method comprising: depositing an unprintable layer (2) on the substrate, imprinting a two-dimensional grid mask (5) into the unprintable layer by a mould (3); directionally depositing a first material (8) in the first direction on the grid mask; and directionally depositing a second material (15) in the second direction on the grid mask, the grid mask acting as a shadow mask during the directional deposition of the first and second material.

Abstract: In order to provide a communication system as well as a vehicle comprising such a communication system for communication between and among vehicles and a method for communication between and among vehicles moving in any different directions within the same area by means of at least one channel designed for transmitting at least one message, the channel comprising at least one code for communication of the vehicles within at least one cluster in which at least one group of vehicles are clustered, wherein interference is to be eliminated, the vehicle comprises directional antennas oriented in different directions in relation to the moving direction of the vehicle to enable the sending direction of the message to be allocatable to directions in relation to the moving direction of the vehicle and the channel is assigned to direction areas, north, east, south and west.

Abstract: A data processing system, circuit arrangement, and method to communicate data over a multi-channel serial communications interface (14) using a dedicated encrypted virtual channel from among multiple virtual channels supported by the communications interface (14). Encryption for the dedicated encrypted virtual channel is provided by a hardware encryption circuit (34) that is coupled to the interface, such that encryption may be performed at a relatively low level, and with substantial protection from compromise, particularly along chip boundaries. In one particular application, access control may be provided for a digital data stream using a multi-chip access control scheme that relies on one chip (148) to provide access control over a received digital data stream, with another chip (150) utilized to process the digital data stream once authorized to do so.

Abstract: A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).

Abstract: The present invention relates to an amplifier circuit and system, and to a method of compensating a gain imbalance generated in a complementary amplifier stage with first and second amplifier means (22, 24) in a bridge configuration. A compensation offset current is generated in response to the values of input signals supplied to respective inputs of said first and second amplifier means, and the compensation offset current is injected to a junction node between the inputs of the first and second amplifier means (22, 24). Thereby, it can be ensured that the gain of the first and second amplifier means does not depend on the kind of input signals, i.e. balanced or unbalanced input signals. An automatic gain correction can thus be achieved and the requirement of additional control signals or control terminals for selection of gain control circuits depending on the kind of input source or input configuration of the amplifier circuit can be dropped.

Abstract: A semiconductor device package (10) with a substantially rectangular shape comprising: a die attach pad (12) having a top surface and a bottom surface; a plurality of contact pads (26i-26n) provided in at least four rows that correspond to the rectangular shape of the package, each contact pad having a top surface and a bottom surface; at least two tie bars (18) for supporting the die attach pad until the singulation of the package during manufacturing thereof the tie bars having a top surface and a bottom surface and extending from the die attach pad towards a corner of the package; —a semiconductor die (20) mounted on the top surface of the die attach pad (12) and having bonding pads (44) formed thereon; a plurality of electrical connections between selected ones of the bond pads (44) and corresponding ones of the contact pads (26i-26n); an encapsulation encapsulating the semiconductor die (20), the top surface of the die attach pad (12), the electrical connections, the top surface of the tie bars (18) and

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.

Abstract: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing a first layer of a first predetermined thickness of a spin-on dielectric on the metal layer protected with a plasma deposited silicon oxide SiOx. Next a thin stress relief layer of a second predetermined thickness is disposed on the first layer of spin-on-dielectric. Upon the thin stress-relief layer, a second layer of a third predetermined thickness of spin-on dielectric is deposited. Low-k spin-on dielectrics may include hydrogen silsequioxane (HSQ) and methyl silsequioxane (MSQ).

Abstract: A communications device, such as a cellular telephone, comprises a RF circuit and a PIFA antenna having feed and shorting terminations. An electrically conductive, self supporting member is provided to effect a connection between contact points of the RF circuit and the antenna. The member has at least one feed pillar and a shorting pillar which are substantially permanently connected to respective contact points of the RF circuit, and an antenna interface which forms a pressure connection with the terminations of the antenna.

Abstract: An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores.