Abstract: An electronic circuit has an inductor. The inductor comprises a first number of electrically conductive tracks (108, . . . ) in, or on, a substrate (105). The tracks are separated from one another. The inductor comprises a second number of electrically conductive wires (120, . . . ). The ends of each wire contacts two different ones of the tracks. Among the first number of tracks there is at least a specific track that is electrically isolated from the wires upon the wires having been connected. Such an inductor can be made using a standardized track configuration on a substrate, and selectively skipping one or more tracks in order to determine the inductance.

Abstract: A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk1-clko) for at least some of the clock domains, and iii) clock control modules (CCl-CCo), arranged respectively for defining the functional clock signals from the primary clock signals and from control signals (intended for setting the clock control modules (CCl) in a normal mode allowing test data transmission from the corresponding emitter clock domain to at least one receiver clock domain or a shift mode forbidding such a test data transmission).

Abstract: An antenna (1, 41) for an RFID transponder (20), comprises a first antenna arm (2, 42), a second antenna arm (3, 43), and a dc-loop structure (14) electrically connected to the first antenna arm (2, 42) at a first connection (15) and to the second antenna arm (3, 43) at a second connection (16). The first antenna arm (2, 42) comprises a first open end (7) and a first terminal end (8) to be connected to an electronic circuit (21) of an RFID transponder (20) and the second antenna arm (3, 43) comprises a second open end (12) and a second terminal end (13) to be connected to the electronic circuit (21).

Abstract: A method of manufacturing a semiconductor device based on a SiC substrate (12), comprising the steps of forming (201) an oxide layer (14) on a Si-terminated face of the SiC substrate (12) at an oxidation rate sufficiently high to achieve a near interface trap density below 5×1011 cm?2; and annealing (202) the oxidized SiC substrate in a hydrogen-containing environment, in order to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET (10) having improved inversion layer mobility and reduced threshold voltage. It has been found by the present inventors that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. According to the present invention, the deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.

Abstract: A membrane (2) for an electroacoustic transducer (1) is disclosed, wherein a thickness (d) of said membrane (2) and an average Young's modulus (Eavg) of said membrane (2) are chosen in such a way that the critical load (Fbc), which causes the membrane (2) to buckle and/or crinkle, is increased compared to a reference membrane. The reference membrane made of Polycarbonate has the same shape, dimension, and stiffness in its direction of movement (MOV) as said membrane (2). According to the result of investigations on buckling and/or crinkling, said effect occurs with different critical buckling/crinkling loads for membranes of the same shape and dimension, but made of different materials, even when the stiffness of the membranes in their direction of movement—and hence their resonant frequency—is identical.

Abstract: A processor bus has several data processing units, each connected to a line system which acts as a bus having bus segments connected in a separable manner through connection units. Functional units arranged on the bus carry out the information thereof. The functional units may carry out exchanges independently of each other. Conversely, functional units in different groups may carry out information exchanges simultaneously. The connection units define combinatory connections of the signal lines, with physical connections between the connection units provided by the bus segments. The connection units can carry out information exchanges with as many connected functional units as desired. The information path from a functional unit to selected functional units can be multiplexed or switched by toggling simultaneous connections to several functional units or by bridging non-participating functional units.

Abstract: A transmitter and/or receiver includes a single crystal clock oscillator circuit and a sample rate converter (SRC) that selectively generates samples at an alternative frequency for subsequent transmission or decoding. A 40 MHz crystal provides the clock signal for the digital-to-analog and analog-to-digital converters that are used to convert the samples to and from analog form. In an IEEE 802.11-compatible embodiment, the 802.11a compatible 20 MHz OFDM samples are converted to and from analog form directly, whereas a sample rate converter converts the 802.11b compatible 22 MHz DSSS samples to and from 40 MHz samples to provide compatibility with the 40 MHz analog conversions.

Abstract: In an integrated-circuit chip having intercommunicating modular functional units of electrical circuits, wired transmission of sensitive information signals between the functional units of the electrical circuits involves generating a reference signal and coding the sensitive information signals, after being emitted by a generating functional unit in the chip, with the reference signal to disguise the sensitive information represented by the sensitive information signals. The coded sensitive information signals are decoded with the reference signal before the sensitive information signals are received by a processing functional unit in the chip. At least one signal of the reference signal and the decoded sensitive information signals are monitored, and a hacker attack is identified in response to a determination that the decoded sensitive information signal is other than a plausible signal.

Abstract: A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.

Abstract: A semiconductor device has active region (30) and edge termination region (32) which includes a plurality of floating field regions (46). Field plates (54) extend in the edge termination region (32) inwards from contact holes (56) towards the active region (30) over a plurality of floating field regions (46). Pillars (40) may be provided.

Abstract: An electronic device is provided which comprises a plurality of processing units (IP1-IP6), a network-based inter-connect (N) coupled to the processing units (IP1-IP6) and at least one monitoring unit (P1, P2) for monitoring a data flow of at least one first communication path between the processing units (IP1-IP6) and for forwarding monitoring results at least temporarily via at least two separate communication paths (MC1, MC2).

Abstract: The invention relates to a semiconductor device comprising: a substrate (1), the substrate (1) comprising a body (5), the body (5) having a surface, the substrate (1) being provided with an insulating layer (10) on the surface of the body (1);—a conductor (25) with insulating sidewall spacers (22) located in the insulating layer (10), the conductor (25) having a current-flow direction during operation, the conductor (25) having a first width, the insulating sidewall spacers (22) each having a second width being smaller than the first width of the conductor (25), the first width and the second width being measured in a direction perpendicular to the current-flow direction of the conductor (25) and parallel to said surface, the conductor (25) having a first top surface extending parallel to said surface, the insulating sidewall spacers (22) having a second top surface, and airgaps (30) located in the insulating layer (10) adjacent to the insulating sidewall spacers (22), characterized in that the first top surf

Abstract: A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor “Virtual” views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those types of functional units that are too difficult or too costly to physically duplicate. By providing different virtual views to the different clusters of a VLIW processor, the compiler/scheduler can generate more efficient code for the processor, than a processor without virtual views and the physical unit restricted to a subset of the processor's clusters. The compiler/scheduler guarantees that the restrictions with respect to scheduling of operations for functional units with multiple virtual views is met. NON-clustered processors also benefit from virtual views.

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1?, D1?) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

Abstract: The present invention relates to an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement, wherein a lumped element hybrid power divider (12) is provided for splitting input signals of main and peak amplifier stages (20, 30, 40) at predetermined phase shifts and non-equal division rates and at least one wideband lumped element artificial line (Z1, Z2) combined with wideband compensation circuit for receiving said first amplified signal and for applying said predetermined phase shift to said first amplified signal and its higher harmonics. Thereby, the low gain of the peak amplifier is compensated by providing the non-equal power splitting at the input. Moreover, the use of the lumped element hybrid power divider leads to an improved isolation between the input ports of the main and peak amplifiers decreasing final distortions of the output signal.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising silicon which is provided with at least one semiconductor element (T), wherein an epitaxial semiconductor layer (1) comprising silicon is grown on top of a first semiconductor substrate (14), wherein a splitting region (2) is formed in the epitaxial layer (1), wherein a second substrate (11) is attached by wafer bonding to the first substrate (12) at the side of the epitaxial layer (1) provided with the splitting region (2) while an electrically insulating region (3) is interposed between the epitaxial layer (1) and the second substrate (11), the structure thus formed is split at the location of the splitting region (2) as a result of which the second substrate (11) forms the substrate (11) with on top of the insulating region (3) a part (IA) of the epitaxial layer forming the semiconductor body (12) in which the semiconductor element (T) is formed.

Abstract: A phase-change-material memory cell is provided. The cell comprises at least one patterned layer of a phase-change material, and is characterized in that this patterned layer comprises at least two regions having different resistivities. If the resistivity of the phase-change material is higher in a well-defined area with limited dimensions (“hot spot”) than outside this area, then, for a given current flow between the electrodes, advantageously more Joule heat will be generated within this area compared to the area of the phase-change material where the resistivity is lower.

Abstract: A wireless device (400) receives a beacon frame. Using the carrier frequency information included in the beacon frame, a frequency offset value between the wireless device (400) and the wireless host (500) is determined. Based on the frequency offset value, a clock drift value between the host clock (504) in the wireless host (500) and the local clock (406) in the wireless device (400) is determined. The wireless device (400) is then powered up in preparation for receiving a subsequent beacon frame based on the clock drift value between the host clock (504) in the wireless host (500) and the local clock (406) in the wireless device (400).

Abstract: A system comprises a plurality of wireless stations for exchanging data over a wireless network and a coordinator station such an access point. The coordinator station receives a request for a traffic specification from one of the wireless stations. The traffic request comprises a traffic parameter (202) representative of the traffic specification. The coordinator station runs an acceptance algorithm (226) to determine if the request can be met based on the parameter and a current traffic schedule based on other previously granted traffic requests (228). If the new request can be accommodated, a traffic scheduler thereafter generates a new traffic schedule (232, 234) using the Cyclic Executive Model (230).

Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.