Abstract: An insulated gate field effect transistor has a drain region (2,4), a body region (6) of opposite conductivity type and a source region (8) and an insulated gate (14) extending laterally over the body region (6), defining a channel region (30) extending in the body region (6) from a source end adjacent to the source region (8) to a drain end adjacent to a drain end part (26) of the drain region (4). A conductive shield plate (22) is provided adjacent to the drain end for shielding the gate. Embodiments include a shield plate extension (32) extending over the drain region from the shield plate (22) towards the gate (14).

Abstract: A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (10) is provided in which the body comprises a doped semiconductor region (24) adjacent a dielectric region (26). The body may further comprise a doped conductive region separated from the semiconductor region by the dielectric region. The material characteristics of single-crystal strontium titanate when doped in various ways are exploited to provide the insulating, conducting and semiconducting components of a MOS stack. Advantageously, the use of a single body avoids the presence of interface layers between the stack components which improves the characteristics of MOS devices such as field effect transistors.

Abstract: An asynchronous FIFO is provided that determines whether its buffer is primed with at least one data element during a data transfer across clock domains in order to eliminate metastability issues that cause data stalls and interruptions in data flow.

Abstract: In a method and a circuit arrangement for preventing interference pulses in the intermediate frequency signal in an AM receiver comprising a mixer, in which a high frequency signal fed to the mixer is blanked out when interference occurs, it is provided that, while the high frequency signal is blanked out, a filter provided for the intermediate frequency signal is undamped.

Abstract: A method for coded data transmission between a base station (10) and at least one transponder (20) within a wireless data transmission system (1), the method comprising the steps of: —providing a set of symbols (S1 . . . S2n) for encoding data (DD), wherein the set of symbols (S1 . . . S2n) is divided into at least two sub-sets (SS1, SS2), and wherein each symbol (S1 . . . S2n) of the complete set is assigned to one of said at least two sub-sets (SS1, SS2); —encoding said data (DD) using symbols (S1 . . . S2n) of said at least two sub-sets (SS1, SS2), wherein at least one encoded symbol (S1 . . . S2n) comprises several bits; —transmitting each encoded symbol (S1 . . . S2n) within a symbol duration (SD) of an encoded data signal (DS) between said base station (10) and at least one transponder (20), wherein the sub-set (SS1, SS2) assigned to each encoded symbol (S1 . . . S2n) is indicated by a value of at least one bit (LB) of each encoded symbol (S1 . . .

Abstract: An electronic device is provided which comprises a plurality of processing units (IP1-IP6; M1-M4), a network-based interconnect (N) with a plurality of network links (L1-L6) and a network interface (NI; MNI; DNI) which is associated to at least one of the processing units (IP1-IP6; M1-M4) and which serves to couple the processing units (IP1-IP6; M1-M4) to the network-based interconnect (N). The plurality of processing units (IP1-IP6; M1-M4) communicate among each other via a plurality of communication paths (C1-C4). At least two communication paths (C1-C4) are merged along the at least one shared network link (L1-L6) if a combined bandwidth of the at least two communication paths does not exceed an available bandwidth of the at least one shared network link (L1-L6).

Abstract: Switching power supplies are implemented using a variety of methods and devices. According to an example embodiment of the present invention, an arrangement provides power to a circuit by selecting between a first supply and a second supply. The arrangement includes a first circuit that charges a first capacitive element using the first supply and generates a first reference voltage by distributing charge between the first capacitive element and a second capacitive element. The arrangement also includes a first comparator that compares the first reference voltage to a second reference voltage derived from the second supply and a second comparator that compares the first reference voltage to a third reference voltage. The arrangement further includes a power control circuit that selects one of the supplies based on the results of the comparisons.

Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process comprises providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side walls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16).

Abstract: The present invention provides for a dual interface memory arrangement employing the checkered memory mapping formed from combined vertically and horizontally sliced memory mapping, and including 2D access means arranged for access to the mapping memory wherein the said to the access means is arranged such that the access overlaps memory mapped to both interfaces both horizontally and vertically, and which arrangement preferably provides for two DTL channels for each interface wherein a highly efficient unified memory arrangement can be achieved for all processing aspects such as CPU, audio, video and gfx processing.

Abstract: A method of providing a clock frequency to a processor is described. The method in accordance with the invention comprises the step of providing at least one reference signal and the step of determining a control value which relates to a desired first frequency. A second signal that relates to the control value is then used in a subsequent step as an input signal for a noise shaper. Then, a first signal which has the first frequency is generated by combining the output of the noise shaper with one of the at least one reference signals. The first signal is used as a clock frequency of the processor. In a preferred embodiment, one reference signal with a fixed reference frequency is provided. The reference signal is gated or enabled and hold by the output signal provided by a 1-bit noise shaper, whereby the first frequency is generated which is then used as processor clock frequency.

Abstract: A process for fabricating an electronic integrated circuit comprising a multi-layer interconnect stack. A structure (26), such as a MIM capacitor is formed by means of a process that requires the generation of a localized voltage across a nearby primary interconnect line (36) to the substrate. A secondary interconnect path (42) is provided which intersects with the primary interconnect line (36), which is removed after the structure (26) has been formed, so as to create an open circuit in the primary interconnect line (36). Thus, the performance of the circuit is enhanced.

Abstract: An electronic memory component provides a plurality of access-secured sub-areas. Each access-secured memory sub-area has at least one assigned parameter, for example, an address. The memory encrypts the assigned parameters of the access-secured sub-areas in such a way that on the one hand the security of such devices is increased considerably and on the other hand the associated expense and technical complexity are not too great. The encryption allows access to at least one sub-area dependent on at least one further sub-area.

Abstract: A method for improving data communication quality in collocated GSM and WLAN subsystems. The GSM device can spuriously emit third harmonics whose frequencies depends on which GSM channel is presently being used. The WLAN receiver uses OFDM subcarriers that can be interfered with by third harmonics of particular ones of the GSM channels. Which OFDM subcarriers would be adversely affected by a particular one of the GSM channels being in use is computed. Then a corresponding particular OFDM subcarrier is deleted after a FFT process and before Viterbi decoding.

Abstract: An estimated motion vector within image signals to obtain robust motion vectors is provided by creating at least one candidate motion vector for at least one current block within an image of the signal, determining for each of said candidate motion vectors at least one match block within at least one image which is temporally neighboring the image of the current block, detecting if the at least one match block lies at least partially outside the active area of the image, then candidate motion vector is calculated based on at least the shifted current block and the shifted match block and shifting at least the current block and the match block such that the match block lies within the active area of the image.

Abstract: The present invention relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE?VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Abstract: The frame (1) comprises an intermediate layer (5) sandwiched between a first layer (3) with a first pattern and a second layer (4) with a second pattern. Adhesion layers (2,12) are present on the first and second layer (3,4) respectively. The patterns are defined such that bumping portions (31) and a cap (21) are defined. The intermediate layer (5) is continuous and extends over spaces (25) between bumping portions (31) and the cap (21), so as to prevent disintegration. The frame is assembled to a device (50) with an electronic element (52), such as a MEMS element. The cap (21) then encapsulates a cavity (60) over the element (52).

Abstract: In a MIMO receiver, initial solutions using sub-optional decoding algorithm are determined for the symbols transmitted from each of a number of transmit antennas at a given time (100). The initial solutions (Sinit1, . . . , SinitNt) are hard-mapped to the nearest possible symbols of transmission (Sest1, . . . , SestNt). For each of the nearest possible symbols limited areas around them in the constellation plane are defined. A list of candidate symbol vectors (list) is then determined, including only symbols lying within the limited areas of the constellation plane. Finally, a joint decoding technique such as ML-technique is implemented to determine the best of the candidate symbol vectors. The number of the calculations can thus be significantly reduced, without having excessively damaging effects on the symbol error rate.

Abstract: The invention relates to a method and a system for calibrating an analogue I/Q-modulator (2) of a transmitter (3), wherein a calibration signal (s(tk)) is transmitted and an in-phase signal (sI(tk)) and a quadrature-phase signal (sQ(tk)) of the calibration signal (s(tk)) are adjusted by at least one predetermined compensation coefficient (C, D, E) in two calibration steps in at least one compensation measurement set (un, vn, wn), whereby: in a first calibration step, the calibration signal (s(tk)) is adjusted by a first complex compensation value (Cn,1, Dn,1, En,1) and an output signal of the detector circuit (20) is correlated with a harmonic (H1, H2) of said calibration signal (s(tk)) to yield a first complex compensation measurement result (un,1, vn,1, wn,1), in a second calibration step, the calibration signal (s(tk)) is adjusted by a second complex compensation value (Cn,2, Dn,2, En,2) and the output signal of the detector circuit (20) is correlated with said harmonic (H1, H2) of said calibration sign

Abstract: A class D amplifier (1) comprises an input unit (11) for receiving a digital input signal (Vin), a pulse shaping unit (12) for producing pulse shaped signals in dependence of the input signal (Vin), a comparator unit (13) for comparing the pulse shaped signals and producing a comparator signal, a driver unit (14) for producing driver signals in dependence of the comparator signal, a switching output unit (15) for producing a pulse width modulated output signal (Vout) in dependence of the driver signals, and a feedback unit (16) for feeding the output signal (Vout) back to the pulse shaping unit (12). The input unit (11) comprises a clipping control unit (10) for controlling the duty cycle of the pulse width modulated output signal (Vout).

Abstract: The invention is directed to a method for controlling a deceleration process of a DC motor (20), wherein the DC motor (20) is driven by a bridge driver (18) coupled to a power supply (12) intended to provide a supply voltage VDD at a power supply output (14), the method comprising the following steps: applying a deceleration PWM signal to the bridge driver (18) for decelerating the DC motor (20), and controlling the bridge driver (18) such that a motor-induced back current is reduced, if the voltage at the power supply output (14) exceeds a voltage threshold which is higher than VDD.