Abstract: A load line regulated switched-mode power converter supplies an output voltage and an output current to a load. The power converter includes an inductor, a switch coupled to the inductor, a first impedance, a second impedance, and a power converter controller. The power converter controller includes a first sense circuit to obtain momentary information on a first current which flows through the first impedance, and which is related to the output current. A difference between a zero load voltage and the output voltage is determined to obtain a difference level. A second sense circuit supplies further information on a second current which flows through the second impedance, and which is related to the first current. An integrator integrates a difference between the further information and the difference level to obtain a correction signal.

Abstract: An instruction processing circuit includes an instruction decoder, with an instruction input coupled to an instruction source and a control output coupled to the control input of an execution circuit. The instruction decoder includes a predecoding circuit, multiple freezing circuits and multiple sub-decoding circuits. The predecoding circuit has an input coupled to the instruction input and outputs coupled to control inputs of the freezing circuits, which feed the respective parallel sub-decoding circuits. The predecoding circuit detects to which type of instruction a supplied instruction belongs, and controls, dependent on the detected type, to which of the sub-decoding circuits instruction information derived from the supplied instruction will be passed and to which of the sub-decoding circuits supply of instruction information derived from a previously supplied instruction will be frozen.

Abstract: According to an example embodiment, there is a magneto-resistive (MR) sensor having an operation mode and a test mode. The MR sensors comprise a first plurality of first MR elements and a second plurality of second MR elements. A first signal processing unit is connected to the first plurality of first MR elements for generating a first output signal; the first output signal has a first phase. As second signal processing unit is connected to the second plurality of second MR elements for generating a second output signal; the second output signal has a second phase. There is a third signal processing unit or processing the first and second output signals; the third signal processing unit is adapted to activate one of the operation mode and the test mode on the basis of the first and second output signals. When the first and second plurality of first and second MR elements are exposed to a homogeneous magnetic field, the third signal processing unit is adapted to activate the test mode.

Abstract: A signal processing circuit comprising a sigma delta analog to digital converter with a feedback loop that comprises an analog filtering circuit (14) that has a controllable time constant. In a calibration mode, a detector (18) detects a signal strength in a band (34) of frequencies at an output of the sigma delta analog to digital converter. A bandwidth control circuit (19) has an output coupled to a control input of the analog filtering circuit (14), and is arranged to control said time constant dependent on a signal strength in a band (34) of frequencies at the output of the sigma delta analog to digital converter. The band (34) of frequencies is selected so that noise shaped quantization noise density (32) of the sigma delta analog to digital converter rises with frequency.

Abstract: An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level and its lowest (output) level.

Abstract: A power supply network (2) for an integrated circuit is provided, the power supply network (2) comprising a supply grid (4); a plurality of supply pads (6), each supply pad (6) being in electrical contact with an edge of the supply grid (4); a current spreader (8) for at least one of the plurality of supply pads (6), each current spreader (8) being in electrical contact with a respective supply pad (6) and the supply grid (4), each current spreader (8) being sized so that it overlaps with a respective portion of the supply grid (4); and each current spreader (8) having a lower electrical resistance than the supply grid (4). Further embodiments provide an integrated circuit with a power supply network as described above.

Abstract: In order to further develop a communication system (400) as well as a corresponding communication method in such way that a protection of the communication medium (300, 310) from timing failures of a communication controller (120) of a node (100), in particular a limited protection of the communication channel (300, 310) from illegal transmissions in the time domain, can be achieved without providing any bus guardian, it is proposed to prevent any transmission of the node (100) during phases with high susceptibility to illegal transmission, in particular during the communication startup of the communication system (400).

Abstract: A simultaneous multiple channel receiver (“SMCR”) for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.

Abstract: In performing testing on Automatic Test Equipment (ATE) it is a challenge to accurately generate and measure RF (radio frequency) power. In an example embodiment, in a test apparatus used for measuring the input and output characteristics of an amplifier, there is a method for determining test program parameters. The method involves calculating input loss from the test apparatus power source to the input of the amplifier, defining an input loss correction factor. The output loss from the amplifier output to the power meter of the test apparatus is calculated, defining an output loss correction factor. Using the input loss correction factor, a real input power level is determined and using the output loss correction factor, a real output level is determined.

Abstract: The present invention provides a system and a method for improving the wireless local area network (WLAN) throughput performance in a collocated WLAN/Bluetooth system that uses packet traffic arbitration (PTA) to schedule WLAN and Bluetooth transmissions. The method includes detecting a Bluetooth transmission, where the Bluetooth transmission comprises one or more quiet periods; and scheduling a WLAN transmission, where frames of the WLAN transmission are received during the quiet periods of the Bluetooth transmission. The method according to the present invention allows the collocated WLAN to receive a frame send by the access point (AP) and acknowledge its reception without the AP reducing the data transmission rate due to unacknowledged frames. Also, the present invention discloses a mechanism where a collocated Bluetooth device (BTD) and WLAN device can communicate to the AP through a single antenna.

Abstract: In a method of producing an integrated circuit (1, 91, 131) for a transponder (2, 112) a photoresist layer (11) is applied on a first surface (8) of a semiconductor device (3). A patterned mask (14, 94) is generated by lithographically patterning the photoresist layer (11), so that the photoresist layer (11) comprises at least one first via (12, 13). The patterned mask (14, 94) comprises a second surface (17) facing away from the first surface (8). The first via (12, 13) is filled with a first bump (15, 16) by depositing the first bump (12, 13) on the first surface (8). A conductive structure (18, 19, 98, 99, 132) is formed on the second surface (17) of the patterned mask (14, 94). The conductive structure (18, 19, 98, 99, 132) is electrically connected to the first bump (15, 16).

Abstract: In a circuit (1) comprising first and second transmission lines (11,12) with first and second line widths, the transmission lines (11,12) are coupled to each other via a coupling (13,14) with first and second coupling widths at its ends, such that a smaller one of the line widths and a larger one of the coupling widths are combined, and such that a larger one of the line widths and a smaller one of the coupling widths are combined. Such a coupling (13,14) introduces relatively small reflection coefficients, for example for distances between ends of the transmission lines (11,12) smaller than a wavelength of frequency signals to be exchanged via the transmission lines (11,12) and the coupling (13,14). The circuit (1) can then become more compact. The coupling (13,14) may comprise one single taper or may comprise a first taper (13) with a first, larger coupling width and a second taper (14) with a second, smaller coupling width.

Abstract: The invention relates to a magnetoresistive sensor with a triangle made of magnetic sensitive material with three corners with two wiring connections, wherein the three sides of the triangle have different or at least substantially equal length.

Abstract: A method of identifying a traced media playback decoder embedded in a device, wherein data representative of a trace message is included in the content field of a media content file and a trigger string (16) is included in the user data field of the file. The file is input to the decoder, and a traced decoder is arranged and configured to render the trace message in a desired format in response to detection of the trigger string. If the decoder is not the traced decoder, the trigger string will be disregarded and the component will try and process the media content file like a normal media content file, which results in an error.

Abstract: A method of producing time domain sound data (B) from sound parameters (A), the method comprising the steps of: forming first frames, each first frame containing sound parameters representing sound, —forming second frames from the first frames, each second frame containing transform domain sound data derived from the sound parameters, the transform domain sound data of each second frame representing sound having a specific time domain length, and each second frame having a length corresponding with an efficient inverse transform, inversely transforming the second frames into third frames (G1, G2, . . .

Abstract: The invention is directed to a method for controlling a deceleration process of a DC motor (20), wherein the DC motor (20) is driven by a bridge driver (18) coupled to a power supply (12) intended to provide a supply voltage VDD at a power supply output (14), the method comprising the following steps: applying a deceleration PWM signal to the bridge driver (18) for decelerating the DC motor (20), and controlling the bridge driver (18) such that a motor-induced back current is reduced, if the voltage at the power supply output (14) exceeds a first voltage threshold which is higher than VDD. In accordance with the invention the method comprises the following step: if the voltage at the power supply output (14) falls below a second voltage threshold which is lower than the first voltage threshold, terminating controlling the bridge driver (18) such that the motor-induced back current is reduced.

Abstract: In a method of operating a transponder (1, 51) a parallel digital data stream comprised of a plurality of digital data sequences (23-25) is generated by the transponder (1, 51). Then, a plurality of modulated signals (42-44) by modulating each of the digital data sequences (23-25) with a dedicated carrier/subcarrier of a plurality of carriers/subcarriers (26-28) is generated. The modulated signals (42-44) are orthogonal to each other.

Abstract: A mobile device comprising a GPS receiver for receiving GPS signals; a communications receiver for receiving historical ephemeris data from an external server; and a processor configured to determine later ephemeris data from the historical ephemeris data and to determine a GPS position fix from the later ephemeris data. In particular, the later ephemeris data may be valid for a time period greater than any single set of the historical ephemeris data.

Abstract: According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test stimulus data to, and test response data from a module being tested. A global enable signal is provided for placing the modules in a test mode. A control circuit is provided between the global enable signal and an associated module; wherein the control circuit is arranged to control whether or not the global enable signal is passed to its associated module.

Abstract: A software GPS processing arrangement comprising a FIFO buffer for receiving a stream of the GPS signal samples, a memory, a DMA controller for transferring the GPS signal samples from the FIFO buffer to the memory, a CPU running GPS signal processing software configured to retrieve the GPS signal samples from the memory and process them to obtain a position fix, and a counter operating independently of the DMA controller and the CPU for keeping count of the number of streamed GPS signal samples.