Abstract: A double gate transistor on a semiconductor substrate (2) includes a first diffusion region (S2), a second diffusion region (S3), and a double gate (FG, CG). The first and second diffusion regions (S2, S3) are arranged in the substrate spaced by a channel region (CR). The double gate includes a first gate electrode (FG) and a second gate electrode (CG). The first gate electrode is separated from the second gate electrode by an interpoly dielectric layer (IPD). The first gate electrode is arranged above the channel region and is separated from the channel region by a gate oxide layer (G). The second gate electrode is shaped as a central body. The interpoly dielectric layer is arranged as a conduit-shaped layer surrounding an external surface (A1) of the body of the second gate electrode. The interpoly dielectric layer is surrounded by the first gate electrode.

Abstract: The invention relates to a method of manufacturing a field effect transistor, in which a semiconductor body of silicon is provided at a surface thereof with a source region and a drain region of a first conductivity type, which regions are both provided with extensions, and with a gate region situated above the channel region. A pn-junction is formed between the extensions and a neighboring part of the channel region using an amorphizing implantation followed by two implantations of dopants of opposite conductivity type, before the gate region is formed and at an angle with the surface of the semiconductor body which is substantially equal to 90 degrees. A steep and abrupt vertical part of the pn-junction is thus formed with a very low leakage current due to the absence of implantations defects. In some embodiments, a low temperature anneal is used to regrow crystalline silicon.

Abstract: The invention relates to a communication system with at least two communication nodes for the transmission of information via a common transmission medium in a time division multiplex process. During the system start, at least one node is provided for monitoring whether a first signal which utilizes at least one slot in a regular manner is already present in the transmission medium. If a first signal is present, said node is designed for testing this first signal as to its integrity and said node is designed for sending a second signal in the case of an incorrect integrity of the first signal, and a programmable position within the time frame given by the second signal is allocated to the time slot utilized by the first signal.

Abstract: The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus (10) comprising a chamber (12) having a gas input port (14) and a gas output port (16), and means (18) for mounting a silicon substrate within the chamber (12), said apparatus further including a gas source connected to the input port and arranged to provide nitrogen or a noble gas as a carrier gas.

Abstract: An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101, 102) from an active mode to a standby mode.

Abstract: Consistent with an example embodiment, there is a magnetoresistive speed sensor with a permanent magnet and a sensor for a magnetic field for detecting the speed of an object rotating about an x-axis. The magnetoresistive speed sensor is equipped with a measuring direction, in which an external magnetic interference field does not influence the measurement result. The measuring direction is aligned parallel with an x-direction and two sensors are disposed with displacement from one another and normal to the measuring direction.

Abstract: An antenna arrangement having a ground plane (30, 212) a PIFA antenna (15, 240) arranged parallel to the ground plane, and a quarter wave slot antenna (220), arranged to radiate or receive with orthogonal polarisations, the ground plane being rectangular and having higher and lower E field regions (25), caused by use of either of the antennas. The feed (205, 218) of at least one of the antennas is located in the lower E field region caused by the other of the antennas, to provide improved isolation for a compact size. This can be useful for diversity or dual band use, for mobile handset devices.

Abstract: A contact allocation method for a subscriber smart card (300) in a mobile terminal (100) fitted with said card, the mobile terminal including at least first and second electronic modules (130, 140) suitable for communicating with the subscriber smart card (300) using respective first and second communications protocols. To enable the way in which the contacts of the subscriber smart card (300) are allocated to be managed dynamically, the card is connected to the first and to the second electronic modules (130, 140) in alternation by selectively connecting at least one contact (C4) of said card to the first or to the second electronic module (130, 140).

Abstract: In order to improve precision for estimating carrier frequency offset and reduce computing load, the present invention provides a method for estimating carrier frequency offset, which comprises steps of calculating a plurality of corresponding intermediate CFOs, respectively, based on one received sync sequence and one prestored sync sequences stored sync sequence through multi-step calculation, wherein, in each step, one corresponding intermediate CFO is calculated based on said received sync sequence and said pre-stored sync sequence; and weighting said plurality of intermediate CFOs in accordance with channel quality of a channel transmitting said received sync sequence to generate one final CFO. Each of the selected sequence segments may have a length and a mutual distance which are both, at its maximum, the full length of the sync sequence minus 1 so as to improve precision for the intermediate CFOs.

Abstract: The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans-conductance state converting the differential input to a differential output current implementing the logical behavior of the MCML Muller-c element and a second stage operating as a trans-impedance stage being coupled to the first stage. Further, the MCML Muller-c element has peaking circuitry being coupled to the first stage, such that the peaking circuitry and the first stage provide a negative capacitance to the MCML Muller-c element for reducing the damping factor of the MCML Muller-c element.

Abstract: The present invention relates to a method and a device for detecting active spreading codes for a signal in a communication system and estimating power of the active spreading codes. Further, the present invention ensures efficient interference cancellation. Multiple correlations are performed at a single level of a spreading code tree, the produced output samples are then observed at this level during a defined period, and a decision for the activity and power is met for all existing codes via extracting and processing information from these samples. At the correlation step, unitary fast Walsh Hadamard transformation is performed at practically the highest spreading factor in the system.

Abstract: The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer 220 arranged in between the first side 202 and the second side 204 of a substrate 200. After having etched trenches 206 and 206? from the first side, the sacrificial buried layer 220 functions as a stop layer during etching of holes 218 and 218? from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.

Abstract: Circuit arrangement, L[ocal]I[nterconnected]N[etwork] comprising such circuit arrangement as well as method for processing input signals of the LIN In order to further develop a circuit arrangement (100)—for processing at least one input signal (12) from at least one data bus (10) of at least one L[ocal]I[nterconnected]N[etwork] and—for providing the data bus (10) with at least one output signal (18), as well as a corresponding operating method in such way that E[lectro]M[agnetic]E[mission] performance and/or E[lectro]M[agnetic]I[mmunity] performance of the L[ocal]I[nterconnected]N[etwork] (300) is improved, it is proposed to provide—at least one analog-digital converting means (ADC) for converting the analog input signal (12) into at least one digital signal (14) to be processed, and—at least one digital-analog converting means (DAC) for converting the processed digital signal (16) into the analog output signal (18).

Abstract: A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysilicon layer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an amorphous layer (86) is created on the substrate (10) so as to improve the Q factor of the inductor (70), without the need for an additional masking step or adverse impact on the polysilicon layer (30).

Abstract: A DC-DC converter is provided with a first estimator unit (RAE, RLPF, RHPF) for performing an accurate control signal estimation and a second estimator unit (FEU, ?VEU) for performing a fast control signal estimation. In addition, a switching unit (SU) is provided for switching to an output of the first estimator unit (RAE, RLPF, RHPF) during almost constant control signal conditions and for switching to an output of the second estimator unit (FEU, ?VEU) during changing control signal conditions to provide an estimation on the required control signal.

Abstract: The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-VT state to a low-VT state.

Abstract: The invention relates to a semiconductor device comprising a substrate (1) and at least one interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20?) and a second wire (20?) which are located in the interconnect layer, the first wire (20?) having a first thickness (T1) and the second wire (20?having a second thickness (T2) that is different from the first thickness, the thickness (T1,T2) being defined in a direction perpendicular to said surface. The invention further relates to a method of manufacturing a semiconductor device comprising a substrate (1) and an interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20?) and a second wire (20) which are located in the interconnect layer.

Abstract: The invention relates to a communication system (1), comprising a digital interface (2) for transmitting data between a medium access control subsystem (3) and a physical layer (4), furthermore comprising at least a vendor specific register (10.3) integrated into the physical layer (4) and accessible by said medium access control subsystem (3) for controlling the physical layer (4), and furthermore comprising at least a system register (9) integrated into the physical layer (4), wherein:—the system register (9) is accessible by the medium access control subsystem (3) via the vendor specific register (10.3).

Abstract: An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallisation layer (120) on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.

Abstract: A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset.