Abstract: An RFID tag (1, 1?) comprises at least one antenna (2, 2?) and electronic tag components (4) cooperating with the antenna, wherein the antenna (2, 2?) and the electronic tag components (4) are positioned on a common substrate (3), wherein portions (3b) of the substrate encircled by the antenna (2, 2?) and not occupied by the electronic tag components (4) have been removed.

Abstract: An Elliptic Curve Cryptography reduction technique uses a prime number having a first section of Most Significant Word “1” states, with N=nm-1+N1B+n0 and a second section with a plurality of “1” or “0” states. The combination of the first section and the second section is a modulus.

Abstract: A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors (10). Configurable multiplexing circuits (12), are placed between IO connections (11a,b) and the IO ports of at least a plurality of the digital signal processors (10). The multiplexing circuits (12) are configured under control of configuration data, so that the multiplexing circuit (12) give the effect of accessing the IO connection only to IO signals from the IO port or ports of one or ones of the respective plurality of digital signal processors (10) that are selected by the configuration data. Preferably, each digital signal processor (10) has its IO part coupled in common to a plurality of the multiplexing circuits (12) separately from the other digital signal processing circuits.

Abstract: A sub-harmonic mixer circuit having an input stage (52) and a current modulating stage (64 is disclosed. The input stage (52) receives an RF input signal (RF+, RF?) at a first frequency and generates output currents (il , i2) varying in dependence upon the Rf input signal. The current modulating stage (64) comprises a first transistor (Q3) for receiving a first local oscillator signal (LO0) respective and a second transistor (Q4) for receiving a second local oscillator signal (LO180), 180 degrees out of phase with the first local oscillator signal, such that a modulating current signal (iO), having twice the local oscillator frequency is superimposed onto the output currents.

Abstract: A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.

Abstract: A non-volatile memory cell on a semiconductor substrate includes a first and a second transistor. Each transistor is arranged as a memory element that includes two diffusion regions capable of acting as either source or drain, a charge storage element and a control gate element. A channel region is located intermediate the two diffusion regions. The charge storage element is located over the channel region, the control gate element is arranged on top of the charge storage element. One diffusion region of the first transistor and one diffusion region of the second transistor form a common diffusion region. The other diffusion region of the first transistor is connected as first diffusion region to a first bit line, the other diffusion region of the second transistor is connected as second diffusion region to a second bit line and the common diffusion region is connected to a sensing line.

Abstract: The present invention relates to receiver apparatuses and methods of controlling weight adaptation in a receiver of a code multiplex telecommunications system with orthogonal spreading codes, wherein received discrete time signal samples are chip-level filtered by using a first equalising step. Additionally, the received discrete time signal samples are delayed by a time period corresponding to a data symbol and used in a second equalising step. Symbol estimates obtained from the first equalising step are non-linearly filtered and used as a desired response for the second equalising step in the following symbol period, wherein equaliser weights adapted in the second equalising step are used for the first equalising step. Alternatively, the second equalising step may be dispensed with and weight adaptation may be incorporated in a single equalising step.

Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

Abstract: The invention concerns a network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network and are designed to adapt their local communication time schedule to the communication time schedule of at least one other network mode, prior to being integrated as active network nodes. A network node to be integrated checks the activity of other network nodes and if no activity is identified, sends out positional messages for other network nodes, said message being fixed by predetermination in its communication time schedule. If a network node cannot be integrated as a reference node, it can only be integrated as an active node if it adapts its local communication time schedule to that of the reference node after receiving positional messages and if a check as to whether its own communication time schedule agrees with the communication time schedules of at least some of the active network nodes proves positive.

Abstract: To enable a method and a system, having at least one base station and/or one data carrier, for transmitting signals between the base station and a number of mobile data carriers operating in the crypto mode or in the plain mode, wherein [a] the base station emits at least one command signal and/or data signal that is provided with at least one identifying pattern, [b] at least one of the data carriers receives the command signal and/or data signal emitted by the base station that is provided with the identifying pattern, [c] at least one of the data carriers that receive the command signal and/or data signal transmits to the base station a response signal that is a response to the command signal and/or data signal, and [d] the base station receives the response signal transmitted by the data carrier.

Abstract: An adjustable impedance matching network comprising passive elements (2, 4, 10, 12) and at least a pair of micro-electromechanical switch-assemblies (6, 8, 14, 16), said switch-assemblies (6, 8, 14, 16) being connected to the passive elements (2, 4, 10, 12) to form parallel circuits and/or serial circuits of said passive elements (2, 4, 10, 12) and said switch-assemblies (6, 8, 14, 16), said circuits having a range of impedance values.

Abstract: The invention refers to a method for monitoring a communication media access schedule of a communication controller (5) of a communication system (1) by means of a bus guardian (6). The communication system (1) comprises a communication media (2) and nodes (3) connected to the communication media (2). Each node (3) comprises a communication controller (5) and a bus guardian (6) assigned to the communication controller (5). Messages are transmitted among the nodes (3) across the communication media (2) based on a cyclic time triggered communication media access scheme.

Abstract: The invention relates to a MEMS resonator comprising a movable element (48), the movable element (48) comprising a first part (A) having a first Young's modulus and a first temperature coefficient of the first Young's modulus, and the movable element (48) further comprising a second part (H) having a second Young's modulus and a second temperature coefficient of the second.

Abstract: A multi-tuner apparatus comprises a splitter (S) for received RF signals. The splitter has a splitter output (U) for connection to a plurality of tuners. To reduce signal degradation and dissipation the output impedance of the splitter output is substantially lower than the input impedance of each of the tuners.

Abstract: Apparatus (200) for driving an LCD display. The apparatus (200) comprises a source driver which is operated between a first power supply rail (VDDH) and a second power supply rail (VSSH). The source driver comprises a power buffer (22) being arranged between the first and the second power supply rails (VDDH, VSSH). The power buffer (22) provides at an output (32) a virtual voltage (VV) of about half the voltage between the two power supply rails (VDDH, VSSH). Furthermore, a P-buffer (20) and an N-buffer (21) are provided. The P-buffer (20) is situated between the first power supply rail (VDDH) and the virtual voltage (VV), and the N-buffer (21) is situated between the virtual voltage (VV) and the second power supply rail (VSSH). The P-buffer (20; 31) is driven at its input side (27) by gamma voltages in an upper voltage regime (VinputP) and the N-buffer (21) is at its input side (28) driven by gamma voltages in a lower voltage regime.

Abstract: A data processing system is provided for processing video data on a window basis. At least one memory unit (L1) is provided for fetching and storing video data from an image memory (IM) according to a first window (R) in a first scanning order. At least one second memory unit (L0) is provided for fetching and storing video data from the first memory unit (L1) according to a second window in a second scanning order (SO). Furthermore, at least one processing unit (PU) is provided for performing video processing on the video data of the second window as stored in the at least one second memory unit (L0) based on the second scanning order (SO). The second scanning order (SO) is a meandering scanning order being orthogonal to the first scanning order (SO1).

Abstract: The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry (30) and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry (30). A bias input of the differential power amplifier circuitry (30) is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry (30). Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.

Abstract: A data processor system is described comprising a first and a second data processor unit (PU1, PU2). The first data processor unit (PU1) has a data source (SW1, IP11, IP 12) for providing data units for transmission to the second data processor unit (PU2) and a retry buffer (RBUF) for temporarily storing transmitted data units. It is provided with a data selector (RSEL) for selecting data units from the data source or from the retry buffer, and a controller (RCTRL) for controlling the data selector, as well as an output (T1x) for providing data selected for transmissions. The second data processor unit (PU2) has an input (R1x) for receiving the transmitted data and an output (PU20) for further transmitting the received data to a third data processor unit. It also has an input buffer (IBUF) coupled to the input, for temporarily storing the received data.

Abstract: An exemplary embodiment of the invention provides a charge pump stage (100) that comprises a first input node (101), a second input node (107), a decoupling capacity (109) having a first terminal (108) and a second terminal (110). Further, the charge pump stage (100) comprises a pump control circuit having a first contact node (102) and a second contact node (111), wherein the first input node (101) is coupled to the first contact node (102). Furthermore, the second input node (107) is coupled to the first terminal (108) of the decoupling capacity (109), and the second terminal (110) of the decoupling capacity (109) is coupled to the second contact node (111) and further coupled to ground (112).

Abstract: The present invention provides for method of seeking synchronization at a data interface between a transmitting element and a receiving element, and to related transmitting and receiving elements of the interface, in which the clock frequency of both elements is the same but which exhibit a phase difference, also known as mesochronous clock domains, the method including the steps of, prior to data transfer at the interface, delivering a strobe signal generated at the transmitting element to the receiving element, generating a strobe signal at the receiving element and synchronizing the same to the strobe signal received from the transmitting element, and maintaining the synchronized strobe signal generated at the receiving element for the sampling of data appearing at the interface from the transmitting element.