Abstract: A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset.

Abstract: The electronic device comprising a RF transistor (100) that is designed for a fundamental RF frequency and that is integrated with an electrostatic protection structure (250) with a further transistor (200). The transistors are suitably MOS transistors, with a gate, source and drain electrodes, and wherein the sources are coupled to a grounded substrate region. The drain region of the further transistor is coupled to the gate of the RF transistor (100), giving rise to a parasitic diode (300) between the drain region of the further transistor and the grounded substrate region under application of a certain input voltage. A filter (350) is present for filtering the fundamental RF frequency from the parasitic diode (300).

Abstract: The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-VT state to a low-VT state.

Abstract: An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallisation layer (120) on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.

Abstract: The present invention concerns a reference voltage generator (40) that provides a reference voltage (Vref new). The voltage generator (30) is operated at a supply voltage (Vdd) being lower than the Silicon bandgap voltage. It comprises a MOSFET transistor (MN; MN3; MP4; MP7) serving as transconductor (Gptat). An input node for feeding a drain current (Iptat) into the drain of said MOSFET transistor (MN; MN3; MP4; MP7) is provided and an output node is connected to the drain and gate of said MOSFET transistor (MN; MN3; MP4; MP7). A current generator (42) allows the MOSFET transistor (MN; MN3; MP4; MP7) to be operated in a specific mode where the drain current (Iptat) has a positive temperature coefficient (?ptat) and the transconductor (Gptat) has a negative temperature coefficient (?ptat).

Abstract: An RF switch circuit (10) and a tuner (12) comprising an RF switch circuit are described. The switch circuit comprises at least two input terminals and one output terminal. The input terminals are connected to different RF signal sources, e. g. a terrestrial TV antenna (16) and a TV cable network (18). The circuit comprises first SPST switches (28, 30), each connected to one of the input terminals and a second, SPDT switch (32) connected to the first SPST switches. The switch circuit achieves high isolation performance between the input terminals (20, 22).

Abstract: A phase-locked loop (PLL) circuit configuration is implemented using a variety of methods and devices. According to one example embodiment, a low power configuration is determined for the PLL circuit which meets a set of desired phase-locked loop circuit characteristics. The PLL circuit (110) has a first frequency-divider (112, 119), a feedback-divider (118) and a fractional-N mode (111).

Abstract: A method of supplying electrical energy from a first electronic circuit (10) to a second electronic circuit (20) connected via a communication interface (30), which interface (30) comprises at least one wire line (31) within a Radio Frequency Identification communication device (1), the method comprising the steps of: providing a coded high frequency data signal (S1) in the first electronic circuit (10); transmitting said coded high frequency data signal (S1) containing data and clock information via said communication interface (30) from said first electronic circuit (10) to said second electronic circuit (20); rectifying the transmitted coded high frequency data signal (S1) via rectifier means (21) in said second electronic circuit (20) to provide a rectified power signal (RS); and supplying the electrical energy contained in the rectified power signal (RS) to the second electronic circuit (20).

Abstract: A device and method for detection of timing errors or failures of a communication controller (24) by a decentralized bus guardian (26) is provided. In a node (20) on a communication network (38), a communication controller (24), a bus guardian (26) and a bus driver (34) operate to receive and transmit information in a designated communication time slot on a communication medium (38). The bus guardian monitors activity on a communication medium and determines if it appears that the communications from other specific nodes on the communication medium are placing information on the communication medium within their designated communication time slots (54). If two or more of the communications from the other specific nodes are operating outside of there designated time slots, then the bus guardian determines that its own related communication controller has a timing failure.

Abstract: An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (VOUT). The third transistor (M3) is coupled between the first node (tn) and the output (VOUT). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3).

Abstract: In a data carrier (1) which includes receiving means (5) for receiving a modulated carrier signal (MTS) which contains a data signal (DS1) encoded in conformity with an encoding method (MA, PW, MI, RTZ, FSK, PSK), demodulation means (9) for demodulating the received modulated carrier signal (MTS) and for outputting the encoded data signal (DS1) contained therein, decoding means (10, 20) for decoding the encoded data signal (DS1) and for outputting data (D1, D2), and data processing means (11) for processing the data (D1, D2) output by the decoding means (10, 20), the decoding means (10, 20) are provided with at least a first decoding stage (12) and a second decoding stage (13), the first decoding stage (12) being arranged to decode a data signal (DS1) encoded in conformity with a first method (RTZ) whereas the second decoding stage (13) is arranged to decode a data signal (DS1) encoded in conformity with a second method (MI).

Abstract: A data processing system is provided. The data processing system comprises at least one processor (P) for processing data according to a set of instructions. The processors are coupled by a bus means (BM). Furthermore, a debugging means (DM) is provided to detect the occurrence of events and the corresponding point of time of the occurrence on the bus means (BM). If predefined events occur at, within and/or after/before predefined points in time, the debugging mode is switched on.

Abstract: It is described a current interface (100, 200) with a blocking capacitor (128, 228). The blocking capacitor (128, 228) is attached to an additional pin (115, 215), thus allowing a supply voltage ripple rejection of an internal sensor circuit (130, 230). The supply lines (160, 260, 170, 270) are decoupled from the capacitor (128, 228) by a diode (125) or by a voltage regulator (226). Thereby, the use of a sensor element (132, 232) with the current interface (100, 200) does not restrict the size of the blocking capacitor (128, 228) because transient times of edges of output current signals of the current interface (100, 200) are not affected by a low-pass behavior of the blocking capacitor (128, 228) combined with a sensing resistor (171, 271) being typically used for measuring the amperage of the output current signals.

Abstract: A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

Abstract: A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.

Abstract: A signal processing circuit has an analog to digital converter (31) for providing a digital signal to a processor (15) from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) controlled by a gain control signal based on detected signal strength. The analog to digital converter has a loop comprising a loop filter for processing the input signal. A signal strength detection circuit (32) is provided for generating the gain control signal, which signal strength detection circuit has loop signal detector for detecting the signal strength from the loop. Hence a received signal strength indicator RSSI is directly coupled to the analog to digital converter (31), avoiding the delay of signal strength detection in the digital processor.

Abstract: Apparatus comprising a charge pump (20) with multiple independently regulated outputs (V1, V2) for providing different voltage levels at each of said outputs. The charge pump (20) comprises a low voltage input (12), on/off regulation (30), and at least two charge stages (11, 21) which arc arranged in a cascaded manner. Each charge stage (11, 21) comprises a stage capacitor (16, 26), a switch (S1, S3), and a buffer (15, 25) for pumping a bottom plate of the stage capacitor (16, 26).

Abstract: An on-state low current detector uses a transistor with main (32) and sense (34) cells. Feedback circuit (36) acts to keep the voltage across main cells (32) at a substantially constant target value when the load current falls below a level that generates the target voltage value in the main cells. The target voltage value is sufficiently high to ensure that the voltages of low current detection comparator (18) are readily measurable.

Abstract: In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as ? ? ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.

Abstract: The delivery of data broadcast over a unidirectional communication data link is targeted at receivers having an environment exhibiting a specific characteristic by labelling the data prior to transmission with a status indicator that defines the characteristic that the local environment of the receiver (17) must possess as a precondition for receiving the data. Typical types of characteristics envisaged are the location of the receiver and the climatic condition of the receiver.