Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which is stored by the store instructions, is loaded by a load operation for the first time. Based on this indication the store instruction is given access directly to the main memory or is routed to main memory through an auxiliary memory.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Abstract: A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the registers and configured to receive input data and selectively deliver the input data to the registers. A data output circuit (340) is coupled to the data registers and configured to selectively output the output data. A selector (350) is coupled to the data input circuit and the data output circuit, and configured to permit the input data it enter selected registers through the data input circuit and permit selected registers to output data through the data output circuit. The invention provides an efficient technique for loading the shift registers without a large number of simultaneous serial shifts. The result is a power-efficient that achieves high performance objectives while minimizing power consumption.

Abstract: An apparatus and method for matched variable resistor structures to electrically measure unidirectional misalignment of stitched masks for etched interconnect layers includes a first test pad and a second test pad for measuring resistance therebetween; a first resistive element electrically connected at a first end to the first test pad; and, a second resistive element electrically connected at a first end to the second test pad. The first resistive element and the second resistive element are electrically connected by a vertical offset. The resistance measured between the first test pad and the second test pad is variable in accordance with an alignment of the first resistive element and the second resistive element relative to the vertical offset. An indicator may optionally provide an indication that the resistive elements are in alignment.

Abstract: The invention relates to an voltage converter for converting a voltage to multiple output voltages, comprising a first switching circuit (SO) connected to an inductive energy storage element (L) for allowing and interrupting a current flow through the inductive energy storage element (L); at least two second switching circuits (S1) for a controllable discharging of the energy stored in the inductive energy storage element (L), each second switching circuit (S1) being connected to the inductive energy storage element (L) in parallel connection to each other at its respective input and each second switching circuit (S 1) comprising a parasitic element; control voltage selection means for selectively supplying a control voltage to the parasitic element of the switching circuits (S1) such that a current flow trough the parasitic element of the respective switching circuit (1) is inhibited when the second switching circuit (S1) is turned off. A negative influence of parasitic elements (e.g.

Abstract: Since parallel MOSFETs are usually driven with one gate signal in power applications, the current sharing between the MOSFETs is automatically established with regard to the characteristics of the individual MOSFETs. This may lead to a large non-uniformity of the current distribution between the MOSFETs. According to the present invention, an individual control of the on-resistances of the MOSFETs is provided, which allows for an improved current sharing between paralleled MOSFETs.

Abstract: A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10). The circuit further includes an output generator (30) coupled to the binary counter and to the clock signal (Ck), the output generator (30) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor.

Abstract: A multi-mode radio module (22) comprises a terminal (11) for connection to an antenna (10). A transmitting branch (DCS/PCS) and a branching circuit are coupled to the terminal (11). The branching circuit comprises at least a first and a second branch for receiving signals in first and second frequency bands (DCS, PCS), respectively. Each of the first and second branches comprise, respectively, a phase shifting circuit (PS1, PS2), a BAW or SAW band pass filter (RXF2, RXF3) coupled to the phase shifting circuit, the bandwidth of the filter being selected to pass a wanted signal in one of the first and second frequency bands but reject an unwanted signal in the other of the second and first frequency bands, and a low noise amplifier (LNA2, LNA3) coupled to an output of the band pass filter. The response of each of the band pass filters (RXF2, RXF3) is phase shifted to present an open circuit at the wanted frequency in the other branch.

Abstract: A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria.

Abstract: A method and apparatus are discloses for wirebonding leads of a plurality of lead frames being part of a lead frame assembly by a wirebonding tool to semiconductor products mounted on the respective lead frames. The semiconductor products are clamped by a clamping mechanism comprising a stationary clamp and a movable clamp. The movable clamp follows the indexing movement of the lead frame assembly during wirebonding of the semiconductor products clamped by the movable clamp. The wirebonding process does not need to be interrupted for the indexing.

Abstract: The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of the present invention does not require mask alignment sensitivity and makes it possible to implant self-aligned an extended drain for erasing of the memory device. Furthermore, the method provides a way of performing separately drain and source implant with different doping without the use of an additional mask.

Abstract: A rake receiver tracks a component of a multipath information signal transmitted over a communication network. The rake receiver aligns and synchronized the component with a locally generated replica of the code sequence that was originally used to spread the information signal at the transmitter side. The rake receiver derives an early de-spread signal using an early shifted version of the replica of the code sequence. The replica is early shifted by a variable delay. The rake receiver also derives a late shifted de-spread signal using a late shifted version of the replica of the code sequence. The replica is late shifted by the same variable delay. The variable delay may be chosen arbitrarily or among a selection of predetermined values. The predetermined values may be selected so that the tracking process is optimized.

Abstract: Consistent with an example embodiment, a trench FET has source regions arranged above insulated gates in trenches. A body region of opposite conductivity type is arranged between the trenches and a body region is arranged above the body region. Source contact metallisation contacts the source and body contact region. In this way a small cell pitch can be achieved.

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (2) which is provided with at least one semiconductor element and the surface of which is provided with an aluminum layer (3) that is patterned by means of a chemical-mechanical polishing process, the side of the device (10) covered with the aluminum layer (3) being pressed against a polishing pad (5), the device (10) and the pad (5) being moved with respect to each other, a slurry (6) containing an abrasive and having a pH level lower than about 12 being applied between the device (10) and the pad (5), and the polishing process being continued till a sufficient amount of the aluminum layer (3) has been removed. According to the invention, the slurry (6) between the device (10) and the pad (5) is provided with a pH level lower than 5 and the pH level is created using merely an acid the aluminum salt of which dissolves well in the slurry (6).

Abstract: The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.

Abstract: A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6?), wherein the material of the insulating layers (6,6?) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.

Abstract: An electronic module MO2 comprises a housing (1) within which an electronic circuit (2) resides, and a mounting tag (15) for mounting the electronic module MO2 on a printed circuit hoard PCB. The mounting tag (15) comprises, from an end towards the housing, a first portion (15A), a second portion (15B) and a third portion (15C). The first portion (15A) has a first width inferior to a second width of the second portion (15B) so as to define a first abutment (16A). The first abutment will come into contact with a printed circuit board PCB when the mounting tag (15) is inserted in a hole (18) of that printed circuit board having a hole width comprised between the first width and the second width. The second width of the second portion 15B is inferior to a third width of the third portion (15C) so as to define a second abutment (16B).