Abstract: Current MAC algorithms impose a significant system performance requirement in order to process messages in real time. According to an exemplary embodiment of the present invention, a hardware implemented generator for generating a MAC is provided, that results in a significant improvement in hardware performance requirements for processing messages in real time. The engine is based on linear feedback shift registers which are adapted to generate secure MACs.

Abstract: An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized.

Abstract: A processing device (D) is dedicated to image frame stabilization of digital video sequences in an electronic equipment (E1), such as a digital camera, for instance. This processing device (D) comprises processing means (PM) arranged, for each current image frame of a video sequence, for determining a type of motion present in the video sequence from global motion parameters of the current image frame and the ones of at least one preceding image frame of this video sequence. These parameters are determined from a motion estimation between the current image frame and the preceding one of the video sequence. The motion determination is followed by a selection of a jitter extraction technique amongst at least two jitter extraction techniques depending on this determined motion type. The jitter extraction technique thus chosen is used to determine a jitter intended to be removed from the determined global motion parameter(s) in order to remove unwanted motion(s) present into the current image frame.

Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.

Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).

Abstract: A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(1), . . . , SA(N); SB(1), . . . , SB(N)). One multi-state circuit (MSCA) switches to a next state in response to a rising edge (Er) in an input signal (OS). The other multi-state circuit (MSCB) switches to a next state in response to a falling edge (Ef) in the input signal (OS). Each multi-state circuit (MSCA, MSCB) has at least one state (SA(1), SB(1)) in which the multi-state circuit inhibits the other multi-state circuit (MSCB, MSCA) so as to prevent the other multi-state circuit from switching to the next state.

Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.

Abstract: The invention relates to a communications network with at least two network nodes, between which data may be transmitted via a transmission medium, in which a communications schedule is provided which allots time slots to the network nodes for access to the transmission medium, in which the network nodes each comprise at least one communication controller with a first scheduler for controlling access by the network nodes to the transmission medium according to the communications schedule, in which the communications network comprises at least one bus guardian with a second scheduler for monitoring accesses by the network nodes to the transmission medium according to a monitoring schedule, in which the communication controller comprises means for generating a local, independent clock signal and a global clock signal, which may be influenced by at least one parameter of the communications system and in which the global clock signal is provided both to control the first schedulers of the communication control

Abstract: In a method for storing and/or changing state information in a memory (2) containing a plurality of memory cells (3), wherein the memory cells (3) assume an irreversible memory state as a result of a programming step, wherein the state information is represented by a number and/or position of memory cells (3) that are in an irreversible memory state or are programmed, the state information (S3, S13) is determined by checking the memory state of the memory, and then, after selecting (S4, S14) an unprogrammed memory cell (3) the selected memory cell is programmed during or for changing the state information of the memory (2).

Abstract: In a transceiver apparatus for use in a multi-frequency communication system a multi-frequency antenna terminal operation allows antenna transmission and reception-modes to be combined. A frequency conversion circuitry has a transmission path and a reception path, wherein each of these paths communicatively connects a signal processor and an antennaswitch. The antenna-switch comprises a multi switch, a transmission-multiplexer and a reception-multiplexer, wherein the antenna switch may be controlled by the signal processor and the multiplexers may be controlled by the signal generator via the multi switch. The antenna has a transmission connector for connecting the transmission path to the antenna and a reception connector for connecting the reception path to the antenna. Advantageous configurations of the transceiver provide an S-loop antenna design and phase matching units in an antenna terminal and a Butler-matrix of the antenna-switch.

Abstract: A receiver (10) is arranged to simultaneously receive at least a first (S1) radio frequency signal having a first frequency band (1) and a second radio frequency signal (S3) having a second frequency band (3) that is at least partly overlapping the first frequency band (1). The receiver has frequency down-conversion means (32,33) for frequency down converting the at least first (S1) and second radio frequency signals (S3) to at least a first (S2) and a second (S4) lower frequency signal and multiplexing means (34) for sequentially multiplexing the at least first (S2) and second lower frequency signals (S4) into a frequency multiplexed signal (S5).

Abstract: A low latency radio/baseband interface protocol is provided. In one embodiment thereof, 8b/10b encoding is used, which has distinct control characters and data characters. Control characters are used to define the beginning of a frame. More particularly, in accordance with one aspect of the invention, signaling between a baseband portion of a communications apparatus and a radio portion of the communications apparatus is achieved by encoding data units of a given number of bits into codes, each code being a data unit of a number of bits greater than the given number of bits. Multiple different types of data exchanges are defined, and a different code is assigned to each type of data exchange. For a given data exchange, a data exchange type is selected in accordance with data to be exchanged, and a message frame is formed in accordance with the data exchange type selected, the message including a code identifying the data exchange type.

Abstract: A method for an up-down converter which is based on a buck converter during the current down-conversion phase (?2, ?3 and ?5, ?6, respectively) of the coil (L1) supplies an output (B) with a relatively high output voltage (UB), where UB>Uin. The down-conversion phase of the coil current (IL1) comprises at least two different down-conversion phases (?2, ?3 and ?5, ?6, respectively). A method for an up-down converter, which converter is based on a boost converter, supplies during the current up-conversion phase (?7, and ?10, respectively) of the coil (L2) an output (D) which has a relatively low output voltage (UD) with power, where UD>Uin. The up-conversion phase of the coil current (IL2) comprises at least two different current reduction phases (?7, ?8 and ?10, ?11, respectively).

Abstract: A router for a network is arranged for guiding data traffic from one of a first plurality Ni of inputs (I) to one or more of a second plurality No of outputs (O). The inputs each have a third plurality m of input queues for buffering data. The third plurality m is greater than 1, but less than the second plurality No. The router comprises a first selection facility for writing data received at an input to a selected input queue of said input, and a second selection facility for providing data from an input queue to a selected output. Pairs of packets having mutually different destinations Oj and Ok are arranged in the same queue for a total number of Nj,k inputs characterized in that Nj,k<N for each j,k.

Abstract: The invention provides a bipolar transistor with an improved performance because of a reduced collector series resistance and a reduced collector to substrate capacitance. The bipolar transistor includes a protrusion (5) which size may be reduced to a dimension that cannot be achieved with lithographic techniques. The protrusion (5) comprises a collector region (21) and a base region (22), in which the collector region (21) covers and electrically connects to a first portion of a first collector connecting region (3). A second collector connecting region (13) covers a second portion of the first collector connecting region (3) and is separated from the protrusion (5) by an insulation layer (10, 11), which covers the sidewalls of the protrusion (5). A contact to the base region (22) is provided by a base connecting region (15), which adjoins the protrusion (5) and which is separated from the second collector connecting region (13) by an insulation layer (14).

Abstract: This invention relates to a semiconductor device for testing and analyzing integrated circuits (1) on a first side and a second side. The semiconductor device (1) having a first surface (A1) and a second surface (A2) both sides having a set of contacts (P3a, P3b, P3a?, P3b?). The sets of contacts on are symmetrically located on positions relative to a first fictitious plane of symmetry (S1) and a second fictitious plane of symmetry (S2). The semiconductor device (1) has at least a first position of use and a second position of use, whereby the second position of use is obtained by rotating the semiconductor device (1) in the first position of use 180° around a fictitious axis (M). This axis (M) is defined by the crossing of the first fictitious plane of symmetry (S1) and the second fictitious plane of symmetry (S2). The semiconductor device thus obtained provides a flexible and generic solution for testing and analyzing integrated circuits on both sides.

Abstract: A device (200) for processing an audio data stream, the device (200) comprising a transient detection unit (201) adapted to detect a transient portion of an audio input data stream (202), and a harmonics generator (203) adapted to generate an audio output data stream (204) based on the audio input data stream (202), the audio output data stream (204) comprising a sequence of harmonics (205) generated only from a non-transient portion of the audio input data stream (202).

Abstract: A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which is stored by the store instructions, is loaded by a load operation for the first time. Based on this indication the store instruction is given access directly to the main memory or is routed to main memory through an auxiliary memory.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.