Abstract: To provide increased security against differential power analysis attacks, a data processing device is provided with a current converter that draws current from an external supply and cyclically apportions drawn current between a charge storage device and a processor such that the drawn current varies independently of the instantaneous power demand of the processor. The data processing device includes: a processor; a charge storage device coupled to the processor; and a current source for supplying the processor with operating current, and adapted to vary its output current independently of the instantaneous power demand of the processor.

Abstract: An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (10a-d), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit (104) and a current modulator (106) coupled to the integrating circuit (104). Each stage triggers a transition in the next stage when the integration result reaches a level defined by a reference voltage. Correlating circuitry (102, 30, 32, 34) is provided with current outputs to generate currents to the current modulators (106) and reference voltages for the saw tooth delay stages (10a-d). The reference voltages are generated at least partly from a common reference (102c), so that noise in the currents from the current modulators (106) and reference voltages is correlated in a way that at least partly cancels the effect of the noise on the delay time.

Abstract: A control unit and a method are provided to reduce an interference pattern in the display of an image on a screen with a pixel frequency. The image is described by pixel data and provided to the screen by a control unit. During the generation of pixel data, the clock signals used in the generation of the pixel data are varied or the pixel frequency is changed.

Abstract: A system (100) for displaying information on a display device (104) comprises; receiving means (202) for receiving services; user interface means (220) for making a user selection of a type of information to be displayed on the display device (104); a filter (206) for selecting a data-element of a first one of the services on basis of the user selection; and rendering means (208) for calculating an output image to be displayed on the display device (104), on basis of output of the filter (206). The system (100) is designed to apply the filter (206) for selecting a second data-element of the second one of the services, on basis of the user selection, when being switched from the first one of the services to a second one of the services, with the data-element and the second data-element being mutually semantically related.

Abstract: A module (100) has test controller (140) for evaluating a functional block (120). The test controller (140) includes a first register (142) coupled between an input pin (162) and an output pin (164) from a plurality of pins (160) and a second register (144) coupled to the first register (142) for capturing an update of the content of the first register (142) responsive to an update signal from a decoder (170). The second register (144) is further arranged to generate evaluation control signals (145). The test controller further includes dedicated control circuitry including a plurality of logic gates (180) and a first logic gate (182). The plurality of logic gates is arranged to decode the content of the first register (142) and provide the first logic gate (182) with a resulting gating signal for blocking the update of the second register (144). Consequently, the dedicated control circuitry is able to prevent undesired changes in the module (100) during an evaluation mode of for instance another module.

Abstract: In a data carrier (1) which includes receiving means (5) for receiving a modulated carrier signal (MTS) which contains a data signal (DS1) encoded in conformity with an encoding method (MA, PW, MI, RTZ, FSK, PSK), demodulation means (9) for demodulating the received modulated carrier signal (MTS) and for outputting the encoded data signal (DS1) contained therein, decoding means (10, 20) for decoding the encoded data signal (DS1) and for outputting data (D1, D2), and data processing means (11) for processing the data (D1, D2) output by the decoding means (10, 20), the decoding means (10, 20) are provided with at least a first decoding stage (12) and a second decoding stage (13), the first decoding stage (12) being arranged to decode a data signal (DS1) encoded in conformity with a first method (RTZ) whereas the second decoding stage (13) is arranged to decode a data signal (DS1) encoded in conformity with a second method (MI).

Abstract: The electronic circuit comprises a functional module (10), a condition signaling module (20), a reference module (30) and a control circuit (40). The condition signaling module (20) generates an indication signal (Imeas) indicative for PVT conditions local to the functional module. The PVT conditions comprise a set of conditions relevant for a module comprising at least one of a voltage supplied to said module, a temperature within an area occupied by said module and the process conditions relevant for said area The reference module (30) generates a reference signal (Iref) having a value that is substantially independent of said PVT-conditions. The control circuit (40) compares the indication signal (Imeas) and the reference signal (Iref), and for generating a control signal (pvt<1>, . . . , pvt<n>) for the functional module.

Abstract: An electric circuit for a communication device (200) for communicating with a further communication device (500), the electric circuit comprising an inductive antenna element (101) adapted for inductively communicating with the further communication device (500), a capacitive antenna element (102) adapted for capacitively communicating with the further communication device (500), and a common matching circuit (105) adapted to match impedances of the inductive antenna element (101) and of the capacitive antenna element (102).

Abstract: A circuit (100) for detecting the duty cycle of clock signals comprises an oscillator (2) whose signal can be changed into a square-wave voltage in a gate (3). In order to obtain a simple construction of the circuit (100) with improved quality of the output signals a low-pass filter (3) is provided whose output signal is situated between “low” and “high”.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).

Abstract: A system and method for detecting the use of pirated software on a processor device (10), whereby said processor device (10) having a bus controller (14), is bonded so as to detect the presence of a signature contained in said software, whereby detection of said signature using said bus controller (14) disables said processor (10).

Abstract: In a radio including analog and digital portions, with at least one A/D converter between the analog and digital portions, and the selectivity of the radio at least partly implemented in the digital domain, an AGC controller sets a first variable gain amplifier (VGA) (302) to low gain upon a determination that a wide-band power estimation exceeds a wide-band threshold. The wide-band threshold is selected to reduce the occurrence of A/D converter saturation. If the wide-band power estimation is less than the wide-band threshold, then for each VGA (302) in the analog portion, a determination is made whether a narrow-band power estimate exceeds a narrow-band threshold, corresponding to that VGA (302), plus a hysteresis value, in which case that VGA (302) is set to low gain; or whether the narrow-band energy estimate is less than the narrow-band threshold minus a hysteresis value, in which case that VGA (302) is set to high gain.

Abstract: In order to further develop a circuit arrangement for as well as a method of performing at least one operation, in particular at least one cryptographic calculation, wherein the problem of creating at least one key, in particular the R[ivest-]S[hamir-] A[dleman] key, satisfying at least one defined digital signature laws, in particular satisfying the German Digital Signature Law, is solved it is proposed that at least one, preferably two, prime numbers (p; q) for key generation, in particular for R[ivest-]S[hamir-]A[dleman] key generation, are searched in compliance with at least one defined digital signature law, in particular with the German Digital Signature Law.

Abstract: A carrier head (100) for a CMP tool, wherein the membrane (108) defining a chamber with a contact surface (102) of the carrier head (100) has a number of integral tubes (110) termining in openings coupled directly to the substrate (106), in addition to a main fluid flow passage (104) coupled to the chamber defined by the membrane (108). In use, during loading and polishing, a vacuum is applied to the main fluid flow passage (104) and the tubes (110) to hold the substrate (106) in flat engagement with the membrane (108) and contact surface (102). In order to unload the substrate (106), fluid pressure is applied to the substrate (106) via the tubes (110), whilst maintaining the application of the vacuum via the main fluid flow passage (104) so as to minimise bending and breakage of the substrate (106).

Abstract: According to an exemplary embodiment a method for securely storing a message comprises dividing a first message into a first plurality of shares, and storing the first plurality of shares on a storing host together with a second plurality of shares of at least a second message, wherein the storing is performed in a mixed manner.

Abstract: An integrated circuit suitable for use at high frequencies and comprising a first capacitor having an input and an output, as well as a ground connection, wherein the capacitor is ESD-protected through an resistor between the capacitor output and the ground connection, which resistor has a resistance value that is sufficiently high so as to prevent any substantial influence on RF performance of the ground connection.

Abstract: In order to further develop a method for summarizing at least one data stream (12) as well as a corresponding data summarization system (100) comprising at least one receiving means (10) for receiving at least one data stream (12) in such way that at least one summary is available immediately after receiving of the data stream (12), in particular immediately after content acquisition and/or recording and/or encoding and/or decoding of the data stream without any post-processing operation, it is proposed to provide—at least one selecting means (30) for selecting part (32, 32?) of the data stream portions and at least one processing means (70) for generating at least one summary by summarizing at least part of the selected data stream portions (32?) in particular until at least one predetermined summary volume is obtained, wherein the summary is generated during the receiving of the data stream (12).

Abstract: A transcoder is described for converting a received first digital signal with a first modulation and encoding scheme to a second digital signal with a second modulation and encoding scheme. The transcoder may include a demodulator that produces a demodulated digital stream of data from the received first digital signal and a modulator in signal communication with the demodulator, where the modulator modulates the digital stream of data with the second modulation and encoding scheme. Additionally, the transcoder may include an upconverter in signal communication with the modulator, where the upconverter produces the second digital signal.

Abstract: In a method for determining filter coefficients of a digital filter, particularly in UMTS, the predetermined filter coefficients bv are divided by a same scaling factor s and then quantized in that counted from the most significant bit onwards only a certain number n of “1” bits is used and in that the quantization error E(s) is minimized by the selection of the scaling factor s0 and these scaled and quantized filter coefficients ?v are implemented in the filter.