Abstract: The disclosure is a routing method for data in a personal area network. The personal area network includes a plurality of nodes. The method includes receiving a frame at a node, determining whether the node contains a routing table entry for the frame destination, and when the node contains a routing table entry, determining a route for the frame based on a first routing protocol. The method further includes, when the node does not contain a routing table entry for the frame destination, determining whether a route should be discovered for the frame destination, and when a route should not be discovered, determining a route for the frame based on a second routing protocol.

Abstract: A signal processing circuit is proposed, which is intended to receive a pair of input signals Sp and Sn in phase opposition on two input terminals and to provide two pairs of output currents SIp and SIn in phase opposition on four output terminals. Each input signal Sp and Sn is amplified in an amplification unit LNAUp and LNAUn and subsequently split in a splitting unit SPLUp and SPLUn. The invention is such that each of the two splitting units SPLUp and SPLUn includes at least two branches, respectively BIp, BQp and BIn, BQn connected between said amplification unit, respectively LNAUp and LNAUn, and one of said output terminals, the four branches BIp, BQp and BIn and BQn each including at least an impedance, respectively RIp, RQp, RIn, RQn, having identical characteristics. Mixer circuits can be easily stacked with this signal processing circuit.

Abstract: Consistent with an example embodiment, the amount of time required for testing circuits that contain a plurality of different clock domains is reduced. According to the embodiment, during selection of the input test pattern to test logic circuits between a timing sensitive flip-flop in a first clock domain that captures a response that depends on test data in a source flip-flop in a second, different clock domain, account is taken of whether the data in the first flip-flop will change value if it is clocked when the response is captured. If not, it may be assumed that uncertainty about the timing relationship of different clock domains does not introduce uncertainty with respect to the data from the timing sensitive flip-flop, so that the response data at the second flip-flop can be treated as reliable.

Abstract: A signal receiver processing circuit for isolating a desired signal from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end, includes a variable gain amplifier, an analog to digital converter, a digital signal processor, and a control unit. The analog to digital converter provides a digital signal to the digital signal processor. The digital signal processor includes a digital filter. The control unit adjusts a filtering accuracy of the analog to digital converter and/or the digital signal processor unit in dependence of a signal quality of the input signal.

Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: An integrated Doherty amplifier structure comprises an input bond pad (IBP), and an output bond pad (OBP). A first transistor (T1) forms the peak amplifier stage of the Doherty amplifier and has a control input (G1) to receive a first input signal (IS1) being an input signal of the Doherty amplifier, and has an output (D1) to supply an amplified first input signal (OS1) at an output of the Doherty amplifier A second transistor (T2) forms a main amplifier stage of the Doherty amplifier and has a control input (G2) to receive a second input signal (IS2) and has an output (D2) to supply an amplified second input signal (0S2). The first input signal (IS1) and the second input signal (IS2) have a 90° phase offset. A first bond wire (BW1) forms a first inductance (L1), and extends in a first direction, and is arranged between the input bond pad (IBP) and the control input (G1) of the first transistor (T1).

Abstract: The present invention relates to a method and apparatus for running an application (APPL) of a mobile device (MB) on an external device (PC). The mobile device comprises an application (APPLI) for running on an operating system (OS_H) of the mobile device, and an emulator (E_M) for emulating the operating system (OS_M) of the mobile device. The method comprises establishing (1, 2) a communication link between the mobile device and the external device (PC); triggering (3) the emulator (E_M) to run on an operating system (OS_H) of the external device (PC); and running the application (APPL) of the mobile device on the emulator (E_M).

Abstract: A GPS RF front-end is disclosed comprising an antenna for receiving GPS signals, an analog to digital converter for sampling received GPS signals and interface circuitry for outputting the GPS signal samples. The GPS RF front-end is configured to vary the sample resolution of GPS signal samples outputted. Also disclosed is a corresponding method of providing a position fix, storage medium and apparatus for the same.

Abstract: Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the ma

Abstract: The present invention relates to emphasizing and de-emphasizing of an analog data signal. Using a main analog driver (14) a data signal indicative of bit values of binary data is converted into a first analog data signal. A second data signal is determined by delaying the data signal a predetermined time interval and inverting the delayed data signal. Using a de-emphasis driver (114), the second data signal are converted into a second analog data signal, wherein the second analog data signal is additive to the first analog data signal if the data signal and the second data signal are indicative of a same bit value, and wherein the second analog data signal is subtractive to the first analog data signal if the data signal and the second data signal are indicative of an opposite bit value. The first analog data signal is emphasized or de-emphasized by superposing the first analog data signal and the second analog data signal.

Abstract: The invention relates to a method of determining a plaintext M on the basis of a cipher C and using a secret key d, wherein the secret key d is used in binary form, wherein the plaintext M is determined in each iteration step i for the corresponding bit di and a security variable Mn is determined in parallel therewith, and then a verification variable x is determined by means of a bit-compatible exponent of the secret key d.

Abstract: An electric circuit for a transponder (110) for communication with a base station (120), the electric circuit comprising a memory unit (111) adapted for storing communication related information, and a processor unit (112) adapted for altering an authentification code necessary for the base station (120) to get access to the memory (111) in accordance with a pseudo-random authentification code altering scheme.

Abstract: The present invention relates to a method for composing a scene containing a plurality of objects, an object comprising chrominance and luminance components, a chrominance value being associated with a set of at least two luminance values, wherein said method comprises a step of blending a first object with a second object resulting in a blended object, said step comprising the sub-steps of:—generating a luminance component of the blended object from the corresponding luminance components of the first and second objects and from a first composition function, and—generating a chrominance component of the blended object from the corresponding chrominance components of the first and second object and from a second composition function, the second composition function depending on a set of associated values of the first composition function.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate enhanced slave/master interfacing on an I2C bus using state machines. The communications system includes a first and second state-machine responsive to the rising edge of the clock signal, and a third state-machine, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal. One of the first state-machine and the second state-machine conform to write states of the communications protocol, and the other of the first state-machine and the second state-machine conform to read states of the communications protocol.

Abstract: A wireless station (102) connecting nodes via a wireless network. The wireless station has a programmable physical layer (204) physically connected to communicate with at least one local node (142); and a controller (212) configured to detect at least one remote node (134) over the wireless network and enable communications between the local node and the remote node. Also there is a wireless network (105) having multiple nodes capable of wirelessly connecting the nodes to the network, having a first wireless station (102) capable of representing more than one remote node and having a programmable 1394 Standard physical layer, the first wireless station physically connected to at least one local node (142) and representing at least one remote node to the local node and a controller (212) configured to detect at least one remote node and enable communications between the local node and the remote node.

Abstract: A receiver (120) is configured to receive data over a communications link. A decapsulator (122) is coupled to the receiver and configured to create datagrams and erasure attributes associated with the datagrams. A decoder (124) is coupled to the decapsulator and configured to store the datagrams in a frame table (400) and to create codewords, the decoder storing the datagrams in table columns to create codewords in table rows, correcting the codewords, and configured to store the erasure attributes in an erasure table (552). The erasure table is characterized in that it comprises a plurality of entries (560), each of which is associated with a column of the frame table. Each entry is comprised of a plurality of elements (570).

Abstract: A gain-controlled low noise amplifier means is provided. The amplifier means comprises an amplifier (T1), a first and second pin diode (D1, D2) coupled in series with opposite forward directions in a negative feedback loop of the amplifier (T1) between an input and an output of the amplifier (T1). The amplifier means furthermore comprises a first current source (IC1) coupled to a node between the first and second pin diode (D1, D2) and a second current source (IC2) coupled to an input of the amplifier (T1).

Abstract: The invention provides a method and a device for determining the temperature of a semiconductor substrate. A resonance circuit (110) is provided on the semiconductor substrate and is formed by a junction capacitor (11) and an inductor (12). The substrate is placed on a holder and the with electromagnetic energy of an electromagnetic field (5) generated by a radiation device (200). A circuit (110) is determined by detecting an effect of the resonance circuit (110) on the irradiated temperature of the semiconductor substrate is determined as a function of the resonance frequency. The method and device according to the invention provide for a more accurate determination of the temperature of the semiconductor substrate due to an increased sensitivity to the temperature of the junction capacitor (11).

Abstract: A method of manufacturing a resistive divider circuit, comprising providing a silicon body (6) having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem (61) supporting a relatively wider silicon platform (62). A silicidation protection (SIPROT) layer (S) is deposited over the body (6) and intermediate taps and then patterned to expose the platform (62). A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.

Abstract: The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11).