Abstract: In a signal processing arrangement, a digital-to-analog converter (DAC1) of the finite impulse response type converts a serial bitstream (BSL) into an analog output signal (AL). The digital-to-analog converter (DAC1) comprises at least two current source arrays (CCA1, CC A2). In a first current source array (CCA1), a current definition cell (CD1) generates a first basic current, and a plurality of first current copy cells ( . . . , CC40, CC41, . . . ) provide respective scaled copies of the first basic current to constitute first filter coefficient currents ( . . . , IP40, IP41, . . . ). In a further current source array (CCA2), a further current definition cell (CD2) generates a further basic current, and a plurality of current further copy cells (CC1, CC2, . . . , CC80) provide respective scaled copies of the further basic current to constitute further filter coefficient currents (IP1, IP2, . . . , IP80).

Abstract: The invention deals with the control of a resonant LLC converter by use of control parameters. The primary current flowing in the resonant tank and a voltage at a predetermined point in the resonant tank are monitored and control parameters are set for a high side conduction interval and control parameters are set for a low side conduction interval, the control parameters for the two conduction intervals being: a peak current of the interval and a predetermined voltage of the interval. The resonant converter comprises series-arranged controllable switches to be connected to the supply source. The resonant converter is operated by setting up criteria for turning off a switch in accordance with criteria including the four control parameters.

Abstract: In order to provide a communication protocol for cryptographic authentication on the basis of at least one cryptographic algorithm, in particular according to the A[dvanced]E[ncryption]S[tandard], by providing at least one random number (PRN?) for at least one first, in particular present, authentication sequence or authentication session (n), and providing at least one further random number (PRN2, PRN3) for at least one further, in particular second or next, authentication sequence or authentication session (n+1), wherein the relevant time for cryptographic authentication is shortened, it is proposed that providing the further random number (PRN2, PRN3) is initialized (p) when, in particular immediately after, successfully performing the authentication in the first authentication sequence or authentication session (n).

Abstract: A communication interface for use in an integrated circuit comprises a clock root circuit (110) configured to receive the clock reference signal and to generate a clock tree signal. A first lane circuit (220b) is coupled to the clock root circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a first interface circuit. A second lane circuit (220a) is coupled to the first lane circuit and configured to receive the clock tree signal and a select signal for selecting a clock signal for a second interface circuit. In one embodiment, each lane circuit includes a buffer (222) configured to receive the clock tree signal and a multiplexer (228) configured to selectively deliver the clock tree signal to the interface circuit. Advantages of the invention include a modular construction of a communication interface having low clock skew.

Abstract: To provide a mobile device which facilitates the sending of a message and decreases the time needed for sending a message, a mobile device is proposed comprising a message creating unit (MCU) which creates a message having one or more message attributes and/or a message content. A recipient database (RDB) stores at least one recipient identification representative of an addressee. An analyzing unit (AU) analyzes the message attributes and/or the message contents, and generates a recipient list of at least one recipient identification based on the analyzed message attributes and/or message contents.

Abstract: The invention relates to a method and a system for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (4) and to an antenna (5), wherein the physical layer (4) comprises a base band (4) with a base band controller (7) and a data processing pipeline (3) comprising a plurality of functional blocks (FB1 . . . 13), comprising the steps of: detecting an end of a frame of payload data, which leaves the antenna (5), at a predetermined point (P1 to P3) within the data processing pipeline (3), especially at the end of the data processing pipeline (3), thereupon, starting a timer (T1) for delaying a de-assertion of an activity signal (PHY_ACTIVE) of the physical layer (4), and after expiration of the timer (T1), de-asserting the activity signal (PHY_ACTIVE).

Abstract: A main memory (10) comprises a plurality of physical blocks of memory locations. The main memory (10) supports erasing of at least a physical block at a time. Pointer information is stored in a subset (40, 42) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block (40) in the subset (40, 42). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block (42) of the subset (40, 42) at least after the first block (40) has been filled. The first block (40) is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset (40, 42) contains a most recent version of the pointing information.

Abstract: A semiconductor device package (10) with a substantially rectangular shape comprising: a die attach pad (12) having a top surface and a bottom surface; a plurality of contact pads (26i-26n) provided in at least four rows that correspond to the rectangular shape of the package, each contact pad having a top surface and a bottom surface; at least two tie bars (18) for supporting the die attach pad until the singulation of the package during manufacturing thereof the tie bars having a top surface and a bottom surface and extending from the die attach pad towards a corner of the package; —a semiconductor die (20) mounted on the top surface of the die attach pad (12) and having bonding pads (44) formed thereon; a plurality of electrical connections between selected ones of the bond pads (44) and corresponding ones of the contact pads (26i-26n); an encapsulation encapsulating the semiconductor die (20), the top surface of the die attach pad (12), the electrical connections, the top surface of the tie bars (18) and

Abstract: A non-volatile memory device (1, 101, 201, 301) having a gap within a tunnel dielectric layer (14, 114, 214, 314) and a method of manufacturing the same is provided. The devices have a stack of layers on top of a substrate (10, 110, 210, 310) including, a charge tunneling layer with a gap (14, 114, 214, 314), a charge storage layer (16, 116, 216, 316), a control gate layer (20, 120, 220, 320) and an insulating layer (18, 118, 218 220) in between the charge storage layer and the control gate. Manufacturing proceeds through deposition of a sacrificial layer (28, 128,228,328) on parts of a substrate, whereupon a stack of layers (24, 124,224,324) including a charge-storage layer, an insulating layer and a control gate layer are formed. Subsequently, selected parts of the sacrificial layer are removed, thereby forming a gap in between the charge storage region and the substrate. The gap is protected from future processing by deposition of a sealing layer (34, 134, 234, 334).

Abstract: An asymmetric semiconductor device (3) that includes an integrated high voltage diode (72), including: a substrate comprising an epitaxial layer (47) and a deep well implant (42) of a first type patterned above the epitaxial layer; a shallow trench isolation (STI) region (46) separating a cathode from an anode; a first well implant (40) of a second type residing below the anode; and a deep implant mask (34) of the second type patterned above the deep well implant and below both the cathode and a portion of the STI region.

Abstract: A broadband antenna structure (10) for a transponder of a radio frequency identification system comprises —a loop resonator (12) with a feedpoint (14) for connecting with an electronic circuit (16), and —a dipole resonator (18) electrically connected to the loop resonator (12) and comprising two electrically isolated legs (20, 22).

Abstract: In enhancing signal quality through packages, meta-materials may be used. Meta-materials are designed to make the signal act in such a way as to make the shape of the signal behave as though the permittivity and permeability are different than the real permittivity and permeability of the insulator used. In an example embodiment, a substrate (10) is configured as a meta-material. The meta-material provides noise protection for a signal line (15) having a pre-determined length disposed on the meta-material. The substrate comprises a dielectric material (2, 4, 6) having a topside surface and an underside surface. A conductive material (30) is arranged into pre-determined shapes (35) having a collective length. Dielectric material envelops the conductive material and the conductive material is disposed at a first predetermined distance (55) from the topside surface and at a second predetermined distance from the underside surface.

Abstract: The present invention relates to a polar modulation apparatus and method, in which an in-phase and a quadrature-phase signal are processed in the analog domain to generate an analog signal corresponding to a derivative of a phase component of said polar-modulated signal. The analog signal is then input to a control input of a controlled oscillator (40). As an example, the processing may be based on a differentiate-and-multiply algorithm in the analog domain. Thereby, phase and envelope signals are generated in the analog domain and bandwidth enlargement due to the processing of the polar signals and corresponding aliasing can be prevented to obtain a highly accurate polar-modulated output signal.

Abstract: A radio frequency interface circuit (11) for a radio frequency identification tag comprising—at least two input terminals (RF+, RF?) for connecting the circuit (10) with an antenna structure of the radio frequency identification tag, —one or more variable resistive loads (14) coupled across pairs of the input terminals (RF+, RF?)—one or more rectifiers (15) each connected on its input side to a pair of input terminals (RF+, RF?) and on its output side to a parallel connection of voltage control means (16) and modulation control means (17), wherein combiner means (18) are provided which are adapted to receive an output signal (19, 20) from the voltage control means (16) and the modulation control means (17), respectively, and to generate a control signal (21) for controlling each variable resistive load (14) depending on the received signals (19, 20) in such a way that each variable resistive load (14) serves as a modulation and voltage regulation circuit, and wherein each variable resistive load is adapted to

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized “hot spot” is obtained.

Abstract: A receiver (30) with an antenna circuit is disclosed, which antenna circuit comprises a coil (31) and either a monopole (35) or a dipole connected to the coil (31). The antenna circuit captures a signal with a wavelength transmitted by a transmitter (1). The coil (31) captures the signal and generates therefrom a current having a frequency corresponding to the wavelength. The coil (31) is dimensioned such that the current is distributed uniformly within the coil (31) at each point in time. Preferably, the monopole (35) or a leg of the dipole has a length corresponding to less than 5% of the wavelength. The invention further relates to a radio transmitter of the same kind. Finally, the invention relates to an RFID tag, a smart card, a mobile device, and a hearing aid, each comprising an inventive receiver (30) and/or an inventive transmitter.

Abstract: The invention relates to a method and a system for estimating a symbol time error in a broadband transmission system, comprising: determination a time error signal of an output-signal of a discrete Fourier-transformation block (5) in a data symbol stream on the basis of intersymbol correlation using a predetermined period in each received symbol, selecting as a predetermined period last samples of a useful data part of an actual symbol and a preceding symbol after the discrete Fourier-transformation, determining the time error value (?) based on the intersymbol interference of the selected samples of the actual symbol and the preceding symbol.

Abstract: A data processing system is provided in a stream-based communication environment. The data processing system comprises at least one processing unit (PU1, PU2) for a stream-based processing of a plurality of processing jobs (J1-J5), a memory means (MEM) having an address range; and a plurality of FIFOs memory mapped to part of the address range of the memory means (MEM), respectively. Each of the FIFOs is associated to one of said plurality of processing jobs (j1-j5) to enable their communication. An address translation unit (ATU) is provided for identifying address ranges in the memory means (MEM) which are not currently used by the plurality of FIFOs and for moving the address range of at least one FIFO to a currently unused address range in the memory means (MEM).

Abstract: An electric counter circuit (30, 40, 80) comprises a clock generator (1, 54, 111, 120, 130) for generating a plurality of clock signals (21-24, 121-125, 131-134) and a sampling device (32, 81) for sampling the clock signals (21-24, 121-125, 131-134) at a first moment in time when a first characteristic signal section (LE) of a digital signal (DS) appears. Furthermore, the circuit (30, 40, 80) comprises a calculation device (33) for calculating the time between the first moment and a second moment which is later than the first moment. This calculation is based on the clock signals (21-24, 121-125, 131-134) at the first moment and based on the clock signals (21-24, 121-125, 131-134) at the second moment. The clock signals (21-24, 121-125, 131-134) each have the same cycle duration (T) and are phase-shifted with respect to each other.