Abstract: The invention provides for an optical disc encoding and decoding system in which in an encode mode the system is arranged to encode Long Distance Code (LDC) clusters from user data and including error correction means for applying error correction to LDC blocks, and interleaving means arranged to form the LDC clusters by interleaving the LDC blocks, wherein the error correction means comprises a plurality of buffers at least one of which is arranged to retrieve data from a SDRAM of the system and to calculate syndromes and at least another of which is arranged to insert parity bytes in the data prior to return to the SDRAM and wherein while the said another of which buffers stores data and calculates syndromes, the said one of which buffers is arranged to insert parity bytes into the data it previously stored, the interleaving means comprising a plurality of buffers arranged for burst access for retrieving data from the SDRAM of the system.

Abstract: A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon layer (10). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon (40) over the sidewall spacers (22) and gate (16), but where the nickel is adjacent to single crystal silicon (10) a layer of NiSi (44) migrates to the surface leaving doped single crystal silicon (42) behind, forming in one step a source, drain, and source and drain contacts.

Abstract: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400).

Abstract: In order to provide an electronic circuit arrangement (100) comprising at least one random number generating unit (10) for generating at least one random number (RN; RN1), wherein a calculation or estimation of the random numbers (RN; RN1) used in software (20) is not possible, especially not by physical measuring methods, at least one additional or second random number generating unit (12) for generating at least one additional or second random number (RN2) is proposed.

Abstract: A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at the end of every output clock. Each divisor bit is gated to a D-input through a respective data multiplexer controlled by a clock output. A run/initialize mode controller receives the input frequency and produces the divided output frequency and controls the timing of the re-initialization.

Abstract: A power semiconductor device is described with a plurality of cells divided into power cells (14) and sense cells (16). A plurality of groups (30, 32) of sense cells (16) are provided. The device allows for compensation of effects caused at the edges of the groups of sense cells (16).

Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less than the handler wafer (304) and drain, a condition under which prior art SOI devices may not properly operate.

Abstract: A receiver (100) adjusts its overall gain based on the detected power level of an incoming signal. The receiver is built with two detectors (D1, D2) which operate with different detecting ranges within the dynamic range of the incoming signal. If the actual power level of the incoming signal falls within one of the resolving ranges, an automatic gain control adjusts the gain of the receiver to a corresponding gain value. If not, the resolving range of one of the two detectors is shifted and eventually reduced to cover the portion of the dynamic range in which the power level is comprised. The gain of the receiver is then temporarily adjusted and a new measurement is carried out by the detector using the new resolving range. The AGC then re-adjusts the gain of the receiver based on the measurement given by the modified detector.

Abstract: An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.

Abstract: A full-adder module (30) comprises a full-adder comprising a plurality of input and output terminals, a sum generation unit and a carry generation unit. The carry generation unit comprises a programmable inverter arranged to selectively invert a carry-in bit to the carry generating unit in response to a control signal applied to one of the input terminals. The full-adder module (30) provides an area-efficient logic block that supports signed multiplications, the logic block retaining its programmable nature and being capable of performing all the other operations it was intended to perform.

Abstract: A semiconductor device and method of its manufacture is disclosed. The device comprises an active semiconductor region (1A) comprising one or more conductive gates (11) and a contact region (1 B) remote from the active region (1A), typically comprising a field oxide region (3). An insulating layer (17) overlies the remote contact region (1 B) and at least a part of the active semiconductor region (1A) with one or more contact windows (19a) formed therethrough at locations between the conductive gates (11). A metallisation contact pad (23) overlying the insulating layer (17) is provided in the remote contact region (1 B). The metallisation contact pad (23) is contacted with a polysilicon contact strip (15) underlying the insulating layer (17) by a conductive pattern of a plurality of filled contact windows (19b) extending across a substantial part of the area of the contact pad (23). In a preferred embodiment, the pattern is a series of filled parallel trenches.

Abstract: A power supply system comprises a parallel arrangement of a linear amplifier (LA) and a DC-DC converter (CO). An output of the linear amplifier (LA) is directly coupled to a load (LO) for supplying a first current (II) to the load (LO). The DC-DC converter (CO) has a converter output coupled to the load (LO) for supplying a second current (12) to the load (LO). The linear amplifier (LA) comprises a first amplifier stage (OS1) to supply the first current (II), and the second amplifier stage (OS2) to generate a third current (13) being proportional to the first current (II). The first amplifier stage (OS1) and the second amplifier stage (OS2) have matched components. The DC-DC converter (CO) further comprises a controller (CON) having a control input for receiving a voltage generated by the third current (13) to control the second current (12) for minimizing a DC-component of the first current (II).

Abstract: The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state (42; 52) of that said circuit wherein all of its own control and messaging signals are taken to their zero level. The present invention claimed relates to the methodology of entering said circuit into this pre-determined state (42;52); where all said signal and messaging lines are taken to zero; thereby reducing power consumption within an electronic circuit when its status is defined as being shut-down or standby.

Abstract: According to one example embodiment, an inductive element is used for power-conversion applications. The inductive element includes a substrate (188) having a first metal layer (190) on the substrate having a thickness greater than one micrometer and arranged as a first set of adjacent non-intersecting conducting segments. There is a ferromagnetic-based body (192) located on the first metal layer that has a ferromagnetic inner core area. At least one other metal layer (198) is on the ferromagnetic-based body and arranged as a second set of adjacent non-intersecting conducting segments. A plurality of conductive vias (194) are located in the ferromagnetic-based body and are arranged to connect respective ones of the first set of adjacent non-intersecting conducting segments to respective ones of the second set of adjacent non-intersecting conducting segments therein providing a contiguous conductive wrap around the inner core area.

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number. By using a DLL to take a timing measurement, the effect of process and temperature variations is reduced by the closed loop feedback of the DLL. In another embodiment, a multiplying DLL (MDLL) is used.

Abstract: With an RFID system for communicating between reading units (R1, R2) and transponders (T1, T2) in at least two different scan areas (S1, S2), wherein at least one reading unit (R1, R2) and at least one antenna (A1-A4, B1-B4) communicating with the reading unit are allocated to each scan area (S1, S2) for the radiation of electromagnetic signals (EA1-EA4, EB1-EB4) in the scan area (S1, S2), the antennas (A1-A4, B1-B4) are designed in such a way that at least one antenna (A1, A3) of a scan area (S1) has a different polarization and/or a different polarization rotation direction relative to at least one antenna (B2, B4) of another scan area (S2).

Abstract: Abstract: A method of estimating a Doppler maximum frequency fd and/or a local oscillator frequency offset f0, the method comprising the steps of: computing a power density spectrum of a received radio signal over a whole frequency range, scanning the computed power density spectrum to determine a frequency sub-range [fmin; fmax] which is not necessarily centered on 0 Hz, the signal power over the sub-range [fmin; fmax] being equal to a predetermined percentage of the signal power over the whole frequency range, and estimating frequency fd and/or offset f0 from frequencies fmin and fmax.

Abstract: An integrated array of non volatile magnetic memory devices, each having a first magnetic layer (10) with a fixed magnetization direction; a free magnetic layer (20) with a changeable magnetization direction; a spacer layer (30) separating the first magnetic layer and the free magnetic layer, and a switch (40) for selecting the device, the layers and at least part of the switch being formed as a columnar structure such as a nanowire. The switch is preferably formed integrally with the columnar nano-structure. By incorporating the switch in the columnar structure with the magnetic layers, the device can be made smaller to enable greater integration. This can be applied to magnetic devices using external fields or those using only fields generated in the columnar structure. A write current can be coupled along the columnar structure in a forward or reverse direction to alter the direction of magnetization of the free magnetic layer according to the direction of the current.

Abstract: There is described a method of manufacturing a damascene interconnect (1) for a semiconductor device. A non conductive diffusion barrier (10) is formed over the wall(s) of a passage (7) defined by a porous low K di-electric material (6) and over the surface of a copper region (3) that closes one end of the passage (7). The non-conductive barrier layer (10) is plasma treated to transform an upper portion thereof (10b) into a conductive layer, while a low portion thereof (10a) comprising material that has penetrated pores of the di-electric material remains non-conductive. The passage (7) is then filled with a second copper region (13) forming an electrical interconnect with the first copper region (3) via the now conductive upper portion (1Ob) of the barrier (10). As a person skilled in the art will know, all embodiments of the invention described and claimed in this document may be combined without departing from the scope of the invention.