Abstract: A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is configured to bypass one or more cores not being tested and to provide the test vector to a core scan chain of the core being tested. The bypassed cores are configured such that the associated shift register circuit portion is driven to a hold mode in which storage elements of the shift register circuit portion have their outputs coupled to their inputs. This method provides holding of the shift register stages when a core is bypassed and in a test mode, and this means the shift register stages are less prone to errors resulting from changes in clock signals applied to the shift register stages.

Abstract: The invention relates to a standby circuit, an electrical device with a standby circuit, a method for the control of the electrical device and a power supply assembly. Whereas the power supply unit and the control electronics are in permanent operation when conventional devices are in the standby mode and consequently have a high power consumption, the invention proposes a solution for saving energy while retaining convenience of operation by which the power supply unit is switched off in the standby mode. A standby circuit, preferably fed by an energy buffer element, remains active in the standby mode and monitors signal inputs for activation events. When an activation event occurs, the standby circuit switches on the power supply unit.

Abstract: A device that supports a plurality n of message objects, including a plurality of registers associated with each message object, including at least one object match ID register that contains a multi-bit object match ID field, and at least one object mask register that contains a multi-bit object mask field; and, a CAN/CAL module that processes incoming messages. The CAN/CAL module assembles a multi-bit screener ID from selected bits of each incoming message to be acceptance filtered, compares the bits comprising the screener ID with corresponding bits of the object match ID field associated with each of at least designated ones of the message objects, disregarding any bits of each object match ID field that are masked by corresponding bits of the associated object mask field, and then determines whether any of the comparisons results in a match.

Abstract: A display device includes pixels arranged in columns and rows, in which the pixels of a row can be selected by means of a row voltage supplied via control lines, and column voltages that correspond to the image data of the selected pixel to be displayed can be supplied via data lines, wherein mutually adjoining pixel groups arranged in a row or column, consisting of adjoining pixels of a row or column, are connected to adjoining control lines or data lines, as applicable, in alternation.

Abstract: In order that an electronic communications system (100) equipped with: [a.1] at least one base station (10), to which [a.2] at least one LC resonant circuit (13, 16) [a.2.1] with at least one antenna unit (16) in the form of a coil, and [a.2.2] at least one capacitive unit (13) series-connected to the antenna unit (16) is assigned, which base station (10) is arranged, in particular, on an object to be secured against unauthorized use and/or against unauthorized access, such as on a means of locomotion, on an access system or on an entry system, and [b.1] at least one transponder station (40), to which [b.

Abstract: An antenna arrangement for a radio communications apparatus such as a mobile phone, comprises a substantially planar patch conductor having a first feed connection point for connection to radio circuitry and a second feed connection point for connection to a ground plane, a first, differential slot in the patch conductor between the first and second connection points and a second, dual band slot located in the patch conductor outside the area between the first and second connection points. The length of the first slot is greater than a quarter wavelength, and provides a third resonant frequency increasing the bandwidth of the antenna. The width of the patch conductor between the first and the second slots is selected to obtain a low impedance transformation and thereby a low antenna resistance causing detuning the antenna. A user holding the phone increases the antenna resistance thereby tuning the antenna.

Abstract: The present invention relates to an impedance transformation circuit (I10; 11a; 11b; 12) with a first contact pad (51) and a second contact pad (52) being spaced-apart and formed on a substrate (20). The impedance transformation circuit comprises at least first circuit element (40) providing a contact area (41) formed on the substrate (20) which is arranged adjacent and between the first (51) and the second (52) contact pad. A first wire element (31) extends over the substrate (20) connecting the first contact pad (51) and a first end portion (41a) of the contact area of the first circuit element (40), whilst at least a second wire element (32) extends over the substrate (20) connecting the second contact pad (52) and a second end portion (41b) of the contact area of the first circuit element (40). The contact area of the first circuit element (40) is shaped such that it is provided a capacitive connection with a predetermined capacitance between the contact area and a fixed reference poteitial.

Abstract: A method for determining rotational error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.

Abstract: A driver for an inductive load such as a solenoid coil 92 includes three FETs 4,6,8. Two of the FETs are reversely connected between battery and output terminals 16, 18, and one of the FETs is connected between output and ground terminals 16, 14. A driver circuit 10 having high and low side control circuitry 58,56 is formed in a common substrate with two of the FETs 4,6. In use, a coil 92 is connected to the output terminal 16, and driven in an energize mode in which current in the coil 92 is built up as indicated by arrow 100, a freewheel mode in which current circulates freely as indicated by arrow 102, and then may be switched off. The reversely connected FETs allow both short circuits to be prevented in the energize mode and allow the coil to be rapidly switched off. In spite of the control circuitry being formed in a common substrate with some of the FETs, the arrangement allows the FETs to be properly driven.

Abstract: The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (10), each device having a floating gate (36), comprising: first forming isolation zones (14) in the substrate (10), thereafter forming a floating gate separator (32) on the isolation zones (14) at locations where separations between adjacent floating gates (36) are to be formed, after forming the floating gate separator (32), forming the floating gates (36) on the substrate (10) between parts of the floating gate separator (32), and thereafter removing the floating gate separator (32) so as to obtain slits in between neighboring floating gates (36). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur.

Abstract: A wireless terminal for use in the transmitting and receiving frequency bands of a frequency duplex system comprises transmitting and receiving stages (Tx, Rx) and signal propagating means (22, 24, 26) coupled to the transmitting and receiving stages. The signal propagating means comprises a narrow band antenna structure (24), such as a Planar Inverted-F Antenna (PIFA), having sufficient bandwidth to cover the larger one of the transmitting and receiving frequency bands and a BAW receiving filter (26) and a BAW transmitting filter (22) coupled by respective feeds to the antenna structure (24). The filters (22, 26) enable the antenna structure to have a small volume and be reusable at different FDD frequencies.

Abstract: The invention relates to a system for generating an output voltage (Vout) from an input voltage (Vup), said system comprising:—regulation means (T1) for regulating said output voltage (Vout) to a target voltage level (Vcons), said regulation means (T1) comprising a control terminal intended to receive a regulation signal (SR) and an output terminal for delivering said output voltage (Vout),—first control means (COMP1) for delivering a first control signal (SC1) from a comparison between said regulation signal (SR) and a first reference signal (Vref1).

Abstract: The integrated capacitor structure comprises a first branch with a first capacitor (60) and a second branch with a second capacitor (70). The second capacitor (70) has a higher capacitance density and a lower breakdown voltage than the first capacitor (60). The first branch has a shorter RC time constant than the second branch, such that a voltage peak will substantially follow the first branch. This first capacitor (60) has a sufficient capacity to store the charge of the voltage peak. In one embodiment, the second capacitor (70) is a stacked capacitor. The structure is suitable for ESD-protection and may, to this end, additionally comprise diodes (21) and resistors (22).

Abstract: The present invention relates to a method and a device (11) using a physical token (14), which provides measurable parameters, to derive at least one data set. A plurality of values of one or more of the parameters are measured. From these measured values, a measure of variance is calculated. Quantization intervals into which a measured value is to be quantized are then determined. A possible value of a data set, which subsequently can be derived from a measured value provided by the physical token, is associated with each quantization interval. Further, information which subsequently enables determination of these quantization intervals is stored. Hence, an enrolling phase has been completed. When the preparing phase has been completed, a deriving phase may commence. When a data set is to be derived, for example to be used as a cryptographic key, a value of any one of the parameters provided by the PUF is measured.

Abstract: In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate (200) having conductive traces (235) and pad landings (265). The conductive traces have pad landings (265). An IC (230) is mounted on the substrate (200). The IC (230) has bonding pads (245). With conductive wires (225), the IC bonding pads (245) are connected to the pad landings (265), which in turn, are connected to the conductive traces (235). A heat slug (220), having predetermined height, is disposed on the substrate surface (200). The heat slug includes a plurality of mounting feet (210) providing mechanical attachment to the substrate. A cavity (220a) in the heat slug accommodates the IC. A plurality of first-size openings (215) surrounds the IC. A second-size opening (255) constructed from one of the first size-openings, is larger than the first-size opening.

Abstract: A method of manufacturing a lateral semiconductor device comprising a semiconductor body (2) having top and bottom major surfaces (2a, 2b), the body including a drain drift region (6a) of a first conductivity type. The method includes the steps of forming a vertical access trench (20) in the semiconductor body which extends from its top major surface (2a) and has a bottom and sidewalls; forming at least one horizontal trench (16) extending within the drain drift region (6a) which extends from a sidewall of the vertical trench (20) in the finished device; and forming a RESURF inducing structure (22) extending within the at least one horizontal trench. In this way, vertically separated lateral RESURF inducing structures are formed without encountering problems associated with known techniques for forming RESURF structures.

Abstract: A storage media for storing data and comprising an integral controller configured to control access to the data depending on the location of the storage media. The storage media may further comprise means to determine its location, e.g. such as a GPS receiver or a cellular network positioning solution. Alternatively, the location may be provided by an external device.

Abstract: A bi-directional switch for a power converter comprises first and second transistors (SW1, SW2) and a floating supply capacitor (C2) associated with the second transistor (SW2). The drive circuit and/or gate of the first transistor (SW1) is charged by the floating supply capacitor (C2) of the second transistor (SW2). The charging takes place at a predetermined moment in the switching cycle, and in particular at a moment in the switching cycle when the voltage across the bi-directional switch is substantially a minimum.

Abstract: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400).

Abstract: A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon layer (10). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon (40) over the sidewall spacers (22) and gate (16), but where the nickel is adjacent to single crystal silicon (10) a layer of NiSi (44) migrates to the surface leaving doped single crystal silicon (42) behind, forming in one step a source, drain, and source and drain contacts.