Abstract: The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said first station repeatedly sends requests for data to the second station. The protocol comprises a first mode for transferring the requests in a first request format at a first communication speed and at least a second mode for transferring said requests in a second request format at a second speed. The second station is arranged to receive requests in a mode selected from a group of modes comprising said first and second modes, and is arranged to give a first indication to said first station if it is arranged to operate according to the first mode and a second indication if it is arranged to operate according to the second mode. The first station comprises a processor, a controller, and a translator. The processor is operable to generate request properties for requests in the first request format.

Abstract: In a method of determining the region of interest in images of skin impressions, the skin having ridges and valleys and the images taking the form of image data, values within a first value range being assigned to the ridges and values within a second value range of the image data being assigned to the valleys, the values of the overall image are shifted in the direction of the first value range. The overall image is split into tiles. Mean values of the shifted values for the individual tiles are compared with a reference value. Those tiles whose mean value deviates relative to the reference value in the direction of the first value range are considered at least on a preliminary basis as belonging to the region of interest.

Abstract: The invention relates to a method of manufacturing a semiconductor device comprising a substrate (1) and a semiconductor body (2) in which at least one semiconductor element is formed, wherein, in the semiconductor body (2), a semiconductor island (3) is formed by forming a first cavity (4) in the surface of the semiconductor body (2), the walls of said first cavity being covered with a first dielectric layer (6), after which, by means of underetching through the bottom of the cavity (4), a lateral part of the semiconductor body (2) is removed, thereby forming a cavity (20) in the semiconductor body (2) above which the semiconductor island (3) is formed, and wherein a second cavity (5) is formed in the surface of the semiconductor body (2), the walls of said second cavity being covered with a second dielectric layer, and one of the walls covered with said second dielectric layer forming a side wall of the semiconductor island (3).

Abstract: The invention relates a method for testing a batch of electrical components like Integrated Circuits, the method involving applying a first test (6) on each electrical component from the batch; and applying a second test (12) on electrical components that have failed the first test (6). Advantageously, the second test (12) is applied directly after the first test (6). Preferably, the first test (6) includes a functional test, and the second test (12) includes a Contact-and-Short-Circuit test.

Abstract: A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.

Abstract: A nonvolatile memory array includes a grid of word lines WL1, . . . ,WL6 and bit lines BL1, . . . ,BL8. Of a plurality of memory cells 210, each memory cell is located at an intersection region of one of the word lines and one of the bit lines. A read/write circuit 280 for reading/writing a data word including a plurality of bits is operative to map each pair of sequential bits of the data word to a respective pair of memory cells located at intersection regions of both a different word line and a different bit line.

Abstract: An array of magnetoresistive memory elements includes a magnetic field sensor for measuring an external magnetic field in the vicinity of the magnetoresistive memory elements. The sensor provides input to enable/disable circuitry that functions to temporarily disable any programming operation when the measured external magnetic field exceeds a threshold value.

Abstract: A system with a transmitter for transmitting digital data via an interface to a receiver. The interface has at least one data line and a clock line. A clock generator supplies a clock signal to the clock line. The receiver uses the clock signal received from the clock line for deriving timing information for processing received digital data. The clock signal may have an amplitude that is lower than the power supply voltage VDD, typically less than half of the power supply voltage, and less stringent requirements can be applied to the waveform of the clock signal than traditionally applied to data and clock signals. The clock signals are hereby less power consuming and cause significantly less electromagnetic interference.

Abstract: The transducer (1) comprises an electrically conductive resonator element (20) extending in a longitudinal direction having a length (l). It can be elastically deformed by an electrically conductive actuator (30) such that the elastic deformation comprises a change of the length (dl). The resonator element (20) is electrically connected to a first contact area (25) and a second contact area (26) thereby constituting a circuit In this circuit the resonator element (20) constitutes a resistor with an ohmic resistance (R) which is a function of the length (l+dl). The transducer (1) further comprises a measurement point (28) electrically connected to the circuit for providing an electrical signal which is a function of the resistance (R).

Abstract: Therefore, an electronic device is provided having a plurality of processing modules (IP1-IP5), an interconnect means (N) for coupling the plurality of processing modules (IP1-IP5) enabling at least one first communication (CII) among the processing modules (IP1-IP5), and at least one first module (D1-D5; NI1-N7) for communicating with one of the plurality of processing modules (IP1-IP5) through the interconnect means (N) based on at least one second communication (CI). A second communication (CI) is established which is non-intrusive with regards to the first communication (CII).

Abstract: A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output cells (72), and is connected to a child TAM, CTAM [0:2]. Each wrapper input cell (75) and each wrapper output cell (72) of the child core is adapted to be connected to the parent TAM, PTAM, in addition to being connected to the child TAM, CTAM, thereby enabling the child core to be placed in the In-test and Ex-test modes at the same time, and allowing the parent and child cores to be tested in parallel.

Abstract: An integrated circuit device has boundary scan structure coupled between a test input and the test output. The test register structure is used to shift information from the test input to a test output. The test shift register structure contains a data shift part coupled to connections for a functional circuit under test. In parallel with the data shift part is an instruction shift structure. By means of test control signals it is controlled whether instruction information travels from the test input to the test output through the instruction shift part or through the data shift part. The instruction shift part controls operation of the device in a test mode. A sensor is provided for sensing a physical operating parameter of the device. The sensor has an output coupled to the shift register structure for feeding a sensing result to the test output from the instruction shift part.

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: A method and arrangement of reducing inter-symbol interference occurring at the digital to analog conversion of a one bit digital signal is provided. During the generation of the one-bit digital signal in a sigma-delta converter the edge-density of the digital signal is measured, the result of the measurement is multiplied with the digital signal and the result of the multiplication is added to the input of the quantizer generating the digital signal. The invention also covers storage media comprising a one-bit digital signal generated in accordance with the invention.

Abstract: A signal processing circuit has an analog to digital converter (31) for providing a digital signal to a processor (15) from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) controlled by a gain control signal based on detected signal strength. The analog to digital converter has a loop comprising a loop filter for processing the input signal. A signal strength detection circuit (32) is provided for generating the gain control signal, which signal strength detection circuit has loop signal detector for detecting the signal strength from the loop. Hence a received signal strength indicator RSSI is directly coupled to the analog to digital converter (31), avoiding the delay of signal strength detection in the digital processor.

Abstract: An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for receiving a pulse of a clock signal (CK) to introduce data thereinto and output said introduced data and a shift register (2), comprising the D flip-flops (F1 to F7) for introducing the data thereinto in accordance with the pulse to output the introduced data, for processing the outputted data from the D flip-flop (F0), wherein the circuit device (1) comprises a control circuit (3) for controlling whether the D flip-flops (F1 to F7) are supplied with the pulse of the clock signal (CK) on the basis of outputted data from the D flip-flop (F0) in accordance with the pulse of the clock signal (CK) and data to be introduced into the D flip-flop (F0) in accordance with the next pulse.

Abstract: Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode portion. The opcode portion specifies an operation to be performed, the number of parameters in the instruction, and definitive characteristics of the parameters. The parameters may represent data which is compressible, thereby enabling the size of parameters in an instruction to be reduced.

Abstract: A time discrete filter comprises a sampling rate converter provided with an input and an output, and a down-sampler having a down-sampling factor nd. The time discrete filter further comprises an up-sampler having an up-sampling factor nu, whereby the up-sampler is coupled to the converter input, and the converter output is coupled to the down-sampler. It has been found that if a sampling rate conversion operation is preceded by an up-sampling operation and only after the conversion is followed by a down-sampling operation to a wanted sampling frequency, that then the complexity in terms of the ultimate number of calculations, in particular multiplications and additions, is reduced. This leads to a decrease of the number of instructions per second which is a measure for the complexity of a Digital Signal Processing (DSP) algorithm.

Abstract: An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit.

Abstract: An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e.g., to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.