Abstract: Polyphase filters comprise a plurality of filters each filter having passive elements. The filters are provided with integrators comprising amplifiers with admittance elements in feedback paths to create one or more other poles not situated on the negative imaginary axis in the plane-zero plot. A conductance element couples an output of an integrator of the integrators to an input of a previous integrator for introducing a frequency shift for at least one pole in the plane pole-zero plot. A capacitor couples an output of the integrator to an input of a next integrator for improving the quality factor of the polyphase filter. A signal inversion allows conductance elements to have negative values necessary for locating at least one pole at the most optimal location in the plane pole-zero plot.

Abstract: In a data carrier (1) that is arranged to receive a signal (S) in a non-contacting manner, there is provided a circuit (2) that is arranged, by using the signal (S), to generate a supply voltage (V) for parts of the circuit (2), the circuit (2) having a storage stage (5) that is arranged to store information capacitively, the information being represented by a value of an information voltage (UI) arising at the storage stage (5), and the circuit (2) having an information-voltage generating stage (6) that is arranged to receive a control signal (CS), which control signal (CS) is of a voltage value that is at most equal to the value of the supply voltage (V), and that is arranged to generate the information voltage (UI) by using the control signal (CS), wherein the information-voltage generating stage (6) has a voltage-raising stage (8) that is arranged to raise the value of the voltage of the control signal (CS).

Abstract: In order to provide a method of determining the signal strength in a receiver or transmitter with complex signal processing using the in-phase channel (I channel) and the quadrature channel (Q channel), by means of which it is also possible to reliably determine the signal strength in receivers with a low intermediate frequency, it is proposed that the field strength signals of the I channel and of the Q channel are fed to an evaluation unit and that, in the evaluation unit, an overall field strength signal is generated on a logarithmic scale without intermediate frequency residues from the individual field strength signals.

Abstract: Receivers (1) comprising television and radio inputs (11,12) for receiving television and radio signals and comprising switching circuits (2) with two first switches (21,22) to be activated in a first mode and located parallelly to the television input (11) and with two second switches (23,24) to be activated in a second mode and located anti-serially to the radio input (12), and control circuits (3) for controlling the switching circuits (2) are modified in such a way that strong radio signals can no longer disturb the television signals. Thereby one of the first switches (21) and one of the second switches (23) together isolate the inputs (11,12) from each other, and the control circuit (3) supplies a first control signal to the first switches (21,22) and supplies a second control signal to non-common points of the anti-serial second switches (23,24). This kind of receivers (1) no longer need different switching circuits (2) for shielded radio inputs and unshielded radio inputs.

Abstract: A trench-gate transistor has an integral first layer of silicon dioxide extending from the upper surface of the semiconductor body over top corners of each cell array trench. The integral first layer also provides a thin gate dielectric insulating layer for a thick gate electrode and the integral first layer also provides a first part of a stack of materials which constitute a thick trench sidewall insulating layer for a thin field plate. Consistent with an example embodiment, there is a method of manufacture. A hardmask used to etch the trenches is removed before providing the silicon dioxide layer. The layer is then protected by successive selective etching of the oxide layer and the nitride layer in the upper parts of the trenches. After the gate electrodes are provided, layers for the channel accommodating regions and source regions may be formed through the oxide layer on the upper surface.

Abstract: In a lead-frame configuration (60), a module (70) and a data carrier (72), two connecting plates (12, 13) of the module (70), which are each intended for connection to a connecting contact or bump (47, 48) of a chip (41), are connected to a reinforcement film (66, 71) formed from a fiber-reinforced film of plastics material by means of a layer (73) of an adhesive that is particularly well suited to transmitting shear forces, in which case there is additionally provided in an advantageous further embodiment, on the reinforcement film (66, 71), at least one further layer (74, 75, 76) that is able to serve for protecting, damping or fastening purposes.

Abstract: The present invention provides a magnetoresistive memory device (30) comprising an array (20) of magnetoresistive memory elements (10) and at least one magnetic field sensor element (32), wherein the magnetoresistive memory device (30) comprises a partial or non-homogeneous shielding means (40, 41) so as to shield the array (20) of magnetoresistive memory elements (10) differently from an external magnetic field than the at least one magnetic field sensor element (32). With “differently” is meant that there is a minimum shielding difference of 5%, preferably a minimum shielding difference of 10%. The present invention also provides a corresponding shielding method.

Abstract: The invention relates to a method of multichannel analog/digital (A/D) conversion, in which in a first and second channel respectively in a first or second channel provision area a first and second analog signal awaiting conversion is sampled by a respective first and second S/H (Sample & Hold) element and the respectively stored sample value thereof is applied as a channel sample to a first and second input of an analog multiplexer for selection, wherein the processing of the respective channel sample then takes place in a processing cycle of all channels by said channel sample being selected in the analog multiplexer by a digital selection control signal for the analog/digital conversion and provided as analog selection signal at an output of the analog multiplexer and after the respective channel provision area being converted in an analog/digital converter.

Abstract: Provided in a circuit (8) for a data carrier (7) are a circuit part (12), which requires a relatively large amount of energy, and at least part of a contact interface (11) via which the circuit part (12) can be supplied with electrical energy, which circuit part (12) is designed to process data signals (DS1, DS2) in a normal-consumption processing mode and in an energy-saving processing mode in which less energy is required than in the normalconsumption processing mode, and which circuit part (12) can be switched into the energysaving processing mode when energy is being supplied via the contact interface (11) and which circuit part (12) can be switched, with the aid of a first mode change signal (MC 1) that can be fed thereto, from the energy-saving processing mode into the normal-consumption processing mode, and further provided in this circuit (8) is at least part of a contactless interface (23) via which a carrier signal (TS) can be received by the circuit (8), and furthermore provided in this circuit (8)

Abstract: What is described is a magnetoresistive sensor for operation with a magnetized encoder, which is equipped with a zone with magnetic north and south poles arranged alternately along a direction of motion, comprising a Wheatstone bridge configuration with a first bridge arm between a first supply terminal and a first signal output terminal of the Wheatstone bridge configuration, a second bridge arm between the first supply terminal and a second signal output terminal of the Wheatstone bridge configuration, a third bridge arm between a second supply terminal and the first signal output terminal of the Wheatstone bridge configuration, and a fourth bridge arm between the second supply terminal and the second signal output terminal of the Wheatstone bridge configuration, wherein each of the bridge arms comprises an ohmic resistance element with a resistance-value dependence on the magnetic field strength of a magnetic field influencing the ohmic resistance element in accordance with a defined characteristic.

Abstract: A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjacent memory elements such that with each control pulse of a row control signal the data words of the memory elements of all rows are shifted in a shift direction into the memory elements of the respectively adjacent row, with the data words of the last row being shifted into the first row, and such that with each control pulse of a column control signal the data words of the memory elements of all columns are shifted in a shift direction into the memory elements of the respectively adjacent column, with the data words of the last column being shifted into the first column, and which are designed such that an external write access is possible only in respect of at least one predefined row and at least one predefined column and such that an external read acc

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

Abstract: A random number generator includes a plurality of groups of independent flip flops, each of the groups having different configurations. Each of the outputs of the plurality of groups of flip flops being connected in an exclusive-or (XOR) arrangement, with a latch connected to the output of the DXOR. A metastable output of at least one of the flip flops causes a random signal to be output by the XOR for random number generation. The groups of flip flops can be divided into equally-sized groups, or unequally-sized groups with different configurations, such as the cross-connecting of NAND gates with or without buffers inserted between the data and clock signals, or inserting buffers between a data line of at least one NAND gate of each of the pairs of NAND gates being connected, or inserting a buffer between clock input of at least one NAND gate of each of the pairs of NAND gates being connected via a buffer. Capacitive loading and cross-connected buffers may also be used to induce varying delays.

Abstract: A transistor amplifier circuit has a current to current feedback transformer for neutralization of feedback capacitance and setting the input impedance of the amplifier. IM3 cancellation is implemented by out-of-band terminations at the input, which does not depend on the loading of the output of the amplifier. The IM3 cancellation contributes better linearity, while the capacitance neutralization contributes high and stable gain. These features are more orthogonal than other prior art techniques in terms of gain and linearity over a wide dynamic range. Hence there is less of a trade-off between the desirable properties of high gain and good linearity. Notably they can be implemented to have good efficiency and high levels of integration, which are important for many applications such as wireless transceivers for portable devices or consumer equipment. The amplifier can be a single ended or a differential common emitter amplifier.

Abstract: A regulator circuit includes a first transistor coupled to a supply voltage and a second transistor coupled between the first transistor and an output node. The regulator circuit also includes a dynamic bias circuit that may selectively provide a bias voltage to a gate of the second transistor. During a first mode such as a low power mode, for example, the bias circuit may provide the bias voltage at a fixed percentage of the supply voltage as the supply voltage varies. In addition, during a second mode such as a high power mode, for example, the bias circuit may provide the bias voltage at a fixed offset from the supply voltage as the supply voltage varies.

Abstract: The present invention provides an array of magnetoresistive memory elements. The array includes means for applying a current or voltage for generating a programming magnetic field at a selected magnetoresistive memory element, a magnetic field sensor unit for measuring an external magnetic field in the vicinity of the selected magnetoresistive memory element, and means for tuning the current or voltage for compensating locally for the measured external magnetic field during a programming operation. The present invention also provides a corresponding method.

Abstract: An apparatus and method for transmitting and receiving an audio signal and/or a video signal with a two-way radio. The two-way radio comprises a transmitter system and a receiver system. The transmitter system is adapted to transmit a digitized video signal and a digitized audio signal. The receiver system is adapted to receive a second digitized video signal and a second digitized audio signal.

Abstract: A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit (18a) and a computational unit. The administration unit of a writing processor maintains information defining a section in the memory which is free for storing data objects for readout by the reading processor. The administration unit of the reading processor maintains information defining a section in the memory in which the writing processor has written completed data for the data objects. The processors are arranged to signal a message to another processor via a processor synchronization channel for updating the information in the administration unit of said other processor.

Abstract: A description is given of a high frequency filter comprising microstrips. The filter comprises at least two resonators (16, 18) which each have, as frequency-determining elements, a first straight microstrip section (28) and a second straight microstrip section (30), which are parallel next to each other, and also a capacitor assembly (22). In each resonator the capacitor assembly is connected between first ends of the microstrip sections and each resonator is exclusively connected to ground at the second ends of the microstrip sections. In each resonator (16, 18) the sum of the two microstrip sections acts as inductive lement. The resonators (16, 18) therefore act in the same manner as a resonator having a single microstrip, the length of which corresponds essentially to the sum of the lengths of the first microstrip section (28) and the second microstrip section (30). This construction of a filter allows a shorter design compared to conventional filter structures.

Abstract: Artifact detection and counting is enhanced using looping in both the horizontal and vertical direction is enhanced via a reduced bandwidth for accumulation of count values into count table entries. According to an example embodiment of the present invention, first and second loops are made for horizontal and vertical count table entries. Quotient and remainder values of a detected artifact value are used for increasing count table entries in the first looping pass, and the count table entries are increased using the quotient value in the second loop. The table increase in the first loop is limited to the length of the remainder value, and the table increase in the second loop is limited to the length of the row or column in the count table being used. In this manner, latency for additions to the count table and the bandwidth for making the additions are reduced, relative to conventional applications. In addition, each entry into the table can be reduced to one addition.