Abstract: Artifact detection and counting is enhanced using looping in both the horizontal and vertical direction is enhanced via a reduced bandwidth for accumulation of count values into count table entries. According to an example embodiment of the present invention, first and second loops are made for horizontal and vertical count table entries. Quotient and remainder values of a detected artifact value are used for increasing count table entries in the first looping pass, and the count table entries are increased using the quotient value in the second loop. The table increase in the first loop is limited to the length of the remainder value, and the table increase in the second loop is limited to the length of the row or column in the count table being used. In this manner, latency for additions to the count table and the bandwidth for making the additions are reduced, relative to conventional applications. In addition, each entry into the table can be reduced to one addition.

Abstract: A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage pipelined network includes first and second stages, where the first stage is disposed intermediate the second stage and the shared resource. First and second arbitration circuits are coupled respectively to the first and second stages of the multi-stage pipelined network, with each arbitration circuit configured to receive requests for access to the resource from at least one initiator and forward such requests to the shared resource.

Abstract: The present invention relates to Current mirror for generating a constant mirror ratio, comprising an output transistor (Tout) having a base, an emitter and a collector, wherein a current flowing through the collector of said output transistor (Tout) constitutes an output current (Iout) of said current mirror and the collector of said output transistor (Tout) is connectable to an output circuit, a buffer transistor having a base, an emitter and a collector, wherein the emitter of the buffer transistor is connected to the base of the output transistor, a buffer current source for providing a fixed buffer current, wherein said buffer current source is connected to the collector of the buffer transistor, and a buffer base voltage control means having an input connected to the base of the output transistor and an output connected to the base of the buffer transistor, wherein the base voltage control means is adapted to controlling a voltage at the base of the buffer transistor in response to a current at the inpu

Abstract: Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the instructions contained in the instruction cache prior to execution of the ISR are overwritten by the ISRs instructions. To reduce trashing of the instruction cache memory, the instruction cache is dynamically partitioned into a first memory portion and a second memory portion during execution. The first memory portion is for storing instructions of the current instruction stream, and the second memory portion is for storing instructions of the ISR. Thus, the ISR only affects the second memory portion and leaves instruction data stored within the first memory portion intact. This partitioning of the instruction cache reduces processor fetch operations as well as reduces power consumption of the instruction cache memory.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which both are provided with extensions (2A,3A) and with a channel region (4) of a second conductivity type, opposite to the first conductivity type, between the source region (2) and the drain region (3) and with a gate region (5) separated from the surface of the semiconductor body (1) by a gate dielectric (6) above the channel region (4), and wherein a pocket region (7) of the second conductivity type and with a doping concentration higher than the doping concentration of the channel region (4) is formed below the extensions (2A,3A), and wherein the pocket region (7) is formed by implanting heavy ions in the semiconductor body (1), after which implantation a first annealing process is done at a moderate temperature and a second annealing

Abstract: Consistent with an example embodiment, there is an electronic circuit for amplification of bipolar symmetric current signals. The electronic circuit has a pair of complimentary current mirrors. Depending on the polarity of the bipolar current signal one or the current mirrors is active while the other current mirror is in an off state. This way adding a biasing current to the input signal is avoided which substantially reduces noise.

Abstract: Consistent with an example embodiment a, DA-converter system comprises the cascade of a multi-bit sigma-delta modulator and a DA-converter. The quantization noise of the sigma-delta modulator is isolated; the isolated quantization noise is word-length reduced in a second noise shaper with frequency independent signal transfer function and the isolated word-length reduced quantization noise is subtracted from the quantization noise of said cascade. In another embodiment, the isolated quantization noise is amplified before and attenuated after the second noise shaper.

Abstract: The microelectromechanical system (MEMS) element (101) comprises a first electrode (31) that is present on a surface of substrate (30) and a movable element (40). This overlies at least partially the first electrode (31) and comprises a piezoelectric actuator, which movable element (40) is movable towards and from the substrate (30) by application of an actuation voltage between a first and a second position, in which first position it is separated from the substrate (30) by a gap. Herein the piezoelectric actuator comprises a piezoelectric layer (25) that is on opposite surfaces provided with a second and a third electrode (21,22) respectively, said second electrode (21) facing the substrate (30) and said third electrode (22) forming an input electrode of the MEMS element (101), so that a current path through the MEMS element (101) comprises the piezoelectric layer (25) and the tunable gap.

Abstract: An integrated circuit comprising a plurality of modules (M1 to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1 to M5, CPU), an interconnect means (IM) for interconnecting said modules (M1 to M5, CPU) and said global memory (GM) based on a plurality of communication services (C1, C2) is provided. Said integrated circuit further comprises at least one communication managing unit (CMU) for managing the communication between said plurality of modules (M1 to M5), wherein said communication managing unit (CMU) receives a request for a communication between at least two of said modules (M1 to M5, CPU) and dynamically selects one of said plurality of communication services (C1, C2) as basis for the requested communication between said modules (MI to M5, CPU).

Abstract: In a method of improving fingerprint images, wherein recorded images are processed on image areas of the fingerprint images by using Gabor filters, the Gabor filters are adapted to characteristic quantities of the image in the relevant image area to be processed.

Abstract: A digital to analog converter including a first current source (3) to which a first digital signal (28,31) is applied for conversion to an analog signal, wherein the first digital signal has a predetermined clock cycle. The digital to analog converter further comprising a second dummy current source (30) associated with the first current source to which a second digital signal (29,32) is applied. The second digital signal is derived from the first digital signal so that in any one clock cycle either the first or the second current source switches. This arrangement has the advantage that the dynamic behavior of the converter is not signal dependent, but dependent only on the clock cycle.

Abstract: The invention relates to a method of packaging an electronic component such as semiconductor device, where by the component is positioned in a cavity of a foil by tweezers and is supported by means of a further foil which is attached to the foil at one side thereof. According to an example embodiment, the component is first placed into the cavity of the foil by the tweezers, and only after that is the further foil positioned adjacent thereto and attached to the foil. The tweezers are moved through the foil to pick up the component, hold it, and move it into the cavity. A feature of this embodiment is that the component may be temporarily supported by a supporting means after being positioned in the cavity and before being attached to the further foil, and the foil with the component is moved in a longitudinal direction (L) of the foil.

Abstract: Apparatus (10) comprising a level shifter (15) connectable to a signal input (1) for receiving an input signal (s(t)) with a negative signal swing. The level shifter (15) provides for a DC shift of the input signal (s(t)) to provide an output signal (r(t)) with positive signal swing. The level shifter (15) comprises an amplifier (17) with a first input (11), a second input (12), and an output (13). A first capacitor (C1), a second capacitor (C2), a reference voltage supply (16), and a transistor (14; 74) serving as a switch, are arranged in a network as follows: the first capacitor (C1) is arranged between the signal input (1) and the first input (11), the second capacitor (C2) is arranged in a feedback-loop (18) between the output (13) and the first input (11), and the reference voltage supply (16) is connected to the second input (12). The transistor (14) is arranged in a branch (19) that bridges the second capacitor (C2), whereby a control signal (CNTRL) is applicable to a gate (14.

Abstract: A system for converting analog wanted signals to digital wanted signals includes an analog filter, an analog-to-digital-converter, and a compensator. The analog filter at least partly suppresses both the analog wanted signals and analog unwanted signals. The compensator is used to compensate the digital output signals for the partly suppressing of the analog wanted signals. A method for converting analog wanted signals to digital wanted signals includes at least partly suppressing both the analog wanted signals and the analog unwanted signals and then compensating the wanted digital signals for the partly suppressing of the analog wanted signals.

Abstract: In the case of a method and a device for transmitting data units by way of a transmission medium that comprises at least three adjacent transmission lines, first of all a plurality of codes is supplied. Each code has a number of code sections that corresponds to the number of transmission lines of the transmission medium. Each code section has on an associated transmission line a predetermined signal value, the sum of the signal values for each transmitted code being substantially constant. For each data unit to be transmitted, a code is selected from the plurality of codes, and the selected code is supplied for transmission by way of the transmission medium. The data units and the codes to be transmitted can be supplied in accordance with a predetermined clock pulse, a new code being selected at each new clock pulse, based on the preceding code and the new data unit.

Abstract: During execution of a program of computer instructions, the execution of branch instructions is detected, and in response, the activity of processing circuitry during execution of instructions following a branch instruction is measured. Respective information about the measured activity is recorded for each of a plurality of branch instructions. The measured activity is later used to adapt the power consumption mode of the processing circuitry after encountering the respective branch instructions.

Abstract: An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.

Abstract: The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5), a second bus master (4) linked to the second bus (6), a first and a second communication channel (7, 20, 8, 21) linking the first and the second bus master (3, 4) with each other, and a control unit (9) controlling the data transfer between the first and the second bus master (3, 4) via the first and the second communication channel (7, 20, 8, 21).

Abstract: In order to provide a phase detector and a method of phase detection which are distinguished by greater sensitivity and simple implementability, at least one differential signal of two input signals (Ua; Ub) may be formed over at least one predefined period by means of a first subtracter (12), at least one maximum value of the at least one differential signal may be detected by means of a first peak detector (16) and at least one minimum value of the at least one differential signal may be detected by means of a second peak detector (18) and at least one further differential signal (Uout) may be formed from the at least one maximum value and the at least one minimum value by means of a second subtracter (14).

Abstract: Sample rate converters (12) for converting input sample rates (F81) of signals into output sample rates (Fs4) are provided with sample rate adapters (3,6) for adapting (basic idea) intermediate sample rates (Fs2) such that output sample rates (Fs4) are larger (upsampling) or smaller (downsampling) than input sample rates (F81), to reduce their complexity and to avoid bookkeeping and structure switching problems. Sample rate adapters (3,6) in the form of variable sample rate decreasers (3) allow the sample rate converters (12) to be used in video applications requiring DC-out being equal to DC-in. Sample rate adapters (3,6) in the form of variable sample rate increasers (6) allow the sample rate converters (12) to be used in audio applications.