Abstract: A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.

Abstract: An amplifier circuit (1) includes an amplifying transistor (QØ) and a dc bias circuit (2) for biasing the amplifier transistor (QØ) to obtain a conduction angle of at least about 180°. The dc bias circuit (2) includes a self-bias boosting circuit which has a Wilson current-mirror (Q4, Q5, Q6) integrated with a cascode current-mirror circuit (Q2, Q3) to form an extended Wilson current-mirror circuit (Q2-Q6) having an output coupled to a control terminal of the amplifying transistor (QØ) by a resistor (R1), and a capacitor (C2) coupled from the extended Wilson current-mirror circuit (Q2-Q6) to a common terminal (Gnd).

Abstract: A memory device is disclosed that has a longer read time than write time and implements a parallel-read operation. The parallel-read operation saves reading time and thus accelerates a write operation that comprises a step of comparing incoming data with memory data that were stored in the memory before. The arrangement is especially applicable to an MRAM memory with 0T1MTJ memory cells. The parallel-read operation involves reading in parallel a large amount of data or all data to be compared from the memory into a first temporary memory. The write data is stored in a second temporary memory. The memory data contained in the first temporary memory is compared with the corresponding write data contained in the second temporary memory and allocated to the same address information. Only that write data is written to the memory, which is different from the corresponding memory data.

Abstract: Methods of providing an estimate of the location of a first device are discloses comprising the steps of determining the location of a separately housed, second device located near to the first device; providing the location of the second device to the first device; and using the location of the second device as an estimate of the location of the first device. Either the second device is arranged to perform a function based on its location other than providing its location as an estimate of the location of the first device, or the location of the second device is provided to the first device using a wireless communications link.

Abstract: The invention relates to a television signal receiver comprising a radio-frequency tuner (1) and at least one subsequent surface-acoustic wave filter (2), in which the radio-frequency tuner (1) filters a RF television signal applied to its input and converts it to an intermediate-frequency television signal which is coupled to the surface-acoustic wave filter (2). The RF tuner (1) has at least one output stage (16) which supplies the IF television signal converted to the intermediate frequency. The output stage (16) is directly connected to an output (6) of the RF tuner (1), while a switch (10) is associated with it, by means of which switch the IF television signal is supplied to a second output (8). A further switch (11) is associated with the second output (8), by means of which switch the associated output (8) is switchable to a fixed reference potential.

Abstract: The invention relates to an echo canceling device and method for an arrangement for transmitting audio signals, in particular uttered speech with an echo filter for canceling echo. The echo filter is arranged between an input channel (1) and an output channel (4). The input channel (1) leads a first electrical input signal to a converter (2) for converting the electrical signal into a first audio signal. The output channel (4) transmits an electrical signal from a converter (3) which converts a second audio signal back into an electrical signal. In order to prevent non-linearly distorted echo in such an echo canceling device or method, a high-pass filter (8) is arranged in the input channel (1) which high-pass filter (8) has a cut-off frequency that is beyond the cut-off frequency of the high-pass behavior in the converter (2). The high-pass filter (8) is followed by a limiting element (9) which limits the amplitude of the input signal to the input range of the converter (2).

Abstract: A switch control circuit (416, 402, 418, 422) and method are provided for transistor-implemented switches (405, 413, 408, 414) of an integrated floating power transfer device (400, 500). The device includes a floating bus (403, 410) driven by a power system which includes a charge pump circuit (419, 408, 414, 420). At least one switch circuit (405, 413) is coupled to the floating bus and the power system for facilitating charging of the floating bus. The switch control circuit (416, 402, 418, 422) includes a level shifting circuit (402) for adjusting a control signal to the at least one switch circuit notwithstanding floating of an input voltage signal thereto to facilitate operation of the switch circuit.

Abstract: A variable-impedance device is placed in parallel with the input to a variable-gain amplifier, and is controlled so as to provide a substantially constant load impedance to a source. Preferably, the variable-impedance device includes a diode with a variable bias current. This diode bias current is adjusted inversely with the amplifier bias current, such that the parallel sum of the two input path impedances remains approximately constant across a wide range of gain. This variable gain amplifier system is particularly well suited for use in a wireless transmitter, or cellular telephone.

Abstract: Disclosed is an AGC detector device and an AGC detecting method for television receivers displaying video pictures consisting of a plurality of horizontal lines to be built up successively, wherein a CVBS signal is inputted which includes horizontal sync pulses having a front porch region and a back porch region and occurring once a horizontal line during a horizontal sync period when generating a current video picture, and further includes vertical sync pulses occurring during a vertical sync period before the generation of a new video picture and including serration pulses which occur during a serration pulse region being part of the vertical sync period. Further, gating pulses are generated having a period which is equal to the line period of the horizontal sync pulses. Said gating pulses are adjusted such that they occur at the back porch region of the horizontal sync pulses.

Abstract: A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).

Abstract: Sub-circuits of an integrated circuit can act as noise sources on common conductors such as power supply lines and the substrate. Each of these conductors may act as a noise medium capable of transferring noise signals from the noise source to other sub-circuits. One or more feedback circuits are coupled between input and output points on opposite sides of where a circuit to be protected is connected to such a medium, so that a output of the feedback circuit is coupled to the noise medium closer to certain noise sources than the input of the feedback circuit. Preferably, multiple feedback circuits are cross-coupled and have transfer connections so that coupling between the input and outputs of different feedback circuit is at least partially suppressed.

Abstract: The invention regards an improved voltage converter with increased current capability. The voltage converter architecture may be configured by software. In the prior art programmable charge pumps have been configured in such a way, that the unused stages were simply short circuited by a decoding logic. According to the invention these stages are used to increase the current capability of the first pumping stage. In particular the result is an increase in current capability of a proposed charge pump device by 10% to 15% without the need of additional parts and within the same area.

Abstract: To improve a method as well as a circuit arrangement (100) for detecting the ground offset of parts of a network system, more particularly for checking the ground contact between network control units where data are sent and received over at least one bus system so that, on the one hand, prior to a breakdown event already a warning can be obtained in this respect that the state of the ground connection between the control units is no longer optimal but, on the other hand, ground defects are not shown by mistake, there is proposed 'a! that in the idle state at least one bus line provided for receiving data and/or of at least one receiver line (24), after a predefinable first time period has elapsed, the level voltage (14) of this at least one bus line is scanned and compared with at least one predefinable limit or reference potential value, 'b! in that if the limit or reference potential value is exceeded, at least one ground error signal is generated, and 'c! in that in dependence on the fact whether until a

Abstract: The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined.

Abstract: The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

Abstract: An ID is being calculated in a manner distributed among devices of the user's personal area network (PAN). The devices communicate in a wireless manner. A server runs a simulation of the PAN. If the server and the PAN calculate matching results, it is assumed that the user's ID is correct for purposes of conditional access. The distribution of the calculation of the ID among the user's PAN devices and its, for practical purposes, stochastic nature render the system very hard to hack.

Abstract: A home-control platform and architecture includes a plurality of serial buses that provide communications among processing devices that are connected to the home-control platform. A bus control unit is configured to allocate the buses among the devices that request communications services. The platform supports one or more control processors that provide an interface to legacy devices, user and network interfaces, browsers, and the like. The platform also accepts optional plug-in cards that perform as coprocessors for specific tasks, such as MPEG encoding and decoding, signal processing, video and audio CODECs, and so on. The software architecture employed to support this platform includes the use of a real-time microkernel Operating System (OS) at the control processors that interfaces with the task coprocessors, and interfaces with a standard OS, such as Vxworks, WinCE, or LINUX.

Abstract: In a method of communicating between a communication station (1) and at least one data carrier (2 (DC)) comprising an information data block (IDB) and useful data (UD=N×UDB), an inventorization procedure with successive procedure runs is carried out at least one part of a block region (NKP-IDB) of the identification data block (IDB) not yet known in the communication station (1) and, in addition, specific useful data (n×UDB) are transmitted from each data carrier (2 (DC)) to the communication station (1) in the implementation of the inventorization procedure, such that after termination of the inventorization procedure at least one part of the identification data block (IDB) of each data carrier (2 (DC)) and the associated specific useful data (n×UDB) are known in the communication station (1).

Abstract: To refine an electrical or electronic component having at least one discrete or integrated device formed from a wafer, in plate or disk form, of semiconductive or insulating material, the front face of which device has at least one protruding electrode and is encapsulated by at least one front-face encapsulant, the side faces of which device are at least partly encapsulated by at least one side-face encapsulant, and the rear face of which device is encapsulated by at least one rear-face encapsulant, and to refine a method of producing the same, in such a way that, with the aim of widening the possible uses and applications, electrical contact is made not solely with the front face of the device that is to be housed in the plastics package of very small dimensions, it is proposed that both the side-face encapsulant and the rear-face encapsulant be formed at least partly of layers, but with the layers connected, of electrically conductive material.

Abstract: A charge pump (1) for generating a first output voltage (Vo1) between a first output terminal (E) and a reference terminal (D), and a second output voltage (Vo2) between a second output terminal (F) and the reference terminal (D). The charge pump (1) further comprises a first input terminal (C) for inputting a DC voltage (V), a first storage capacitor (Cr1) coupled between the first output terminal (E) and the reference terminal (D) and a second storage capacitor (Cr2) coupled between the second output terminal (F) and the reference terminal (D). The charge pump (1) further comprises a first terminal (A) and a second terminal (B) for coupling a pump capacitor (Cp) to a first triplet of switches (S1, S2, S5) and to a second triplet of switches (S3, S4, S6). The first triplet of switches (S1, S2, S5) selectively couples the first terminal (A) to either the first input terminal (C) or to the reference terminal (D) or to the second output terminal (F).