Abstract: Aspects of the present disclosure involve negotiating a TWT agreement by communicating which links, of a multi-link system as may be used in WiFi communications, are to be used for negotiating the TWT agreement. This communication may be accomplished, for example, by using fields of the MAC header, individual TWT parameter set, or broadcast TWT parameter set.

Abstract: A method of managing load units of executable instructions between internal memory in a microcontroller with multiple bus masters, and a non-volatile memory device external to the microcontroller. A copy of the load units are loaded from the external memory device into the internal memory for use by corresponding bus masters. Each load unit is with a corresponding load entity queue and each load entity queue is associated with a corresponding one of the multiple bus masters. Each load entity queue selects an eviction candidate from the associated copy of the load units currently loaded in the internal memory. Information identifying the eviction candidate for each load entity queue is broadcasted to all load entity queues. The eviction candidate is added to a set of managed eviction candidates if none of the load entity queues vetoes using the eviction candidate.

Abstract: A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.

Abstract: An automotive control system includes a safety processor and a system-on-a-chip. The SoC includes a primary processor, a safety monitor, first and second GPIO banks, and a debug interface. The safety monitor is configured to detect a fault condition of the primary processor and to provide an indication of the fault condition to the safety processor. The first GPIO bank is coupled to the primary processor to provide input/output operations to a non-critical function of an automobile, while the second GPIO bank is coupled for a critical function of the automobile. The debug interface is coupled to the second GPIO bank to form a scan chain with input and output registers of the second GPIO bank, and is coupled to the safety processor to receive control information for the scan chain to provide input/output operations to the critical function of the automobile when the safety monitor provides the indication.

Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.

Abstract: Aspects are directed to a waveguide structure that can couple to an integrated circuit package. The IC package includes a plurality of pillars to provide a path for carrying millimeter-wave signals, each of the pillars having a first end portion to connect to the IC package and a second end portion to connect to a waveguide antenna. Also, as may be optionally included, waveguide shields provide electro-magnetic isolation for the pillars and a micro-strip connector to provide connection between the second end portions (of the pillars) and to the waveguide antenna. Further included in the apparatus are a plurality of bond wires to connect the IC package and a lead frame, and to carry signals form circuitry of the IC package to the printed circuit board on which the package is mounted for transmission of radar signals via the waveguide antenna.

Abstract: An example method includes controlling a switching order of a plurality of power switches. The power switches are coupled to a flying capacitor and include parasitic bipolar transistors susceptible to the voltage overstress in response to excess stray inductance of the flying capacitor. The method further includes, in response to the controlled switching order, converting an input voltage of a first voltage level to an output voltage of a second voltage level while mitigating the voltage overstress of the parasitic bipolar transistors of the plurality of power switches.

Abstract: A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.

Abstract: A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure.

Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

Abstract: Aspects of the disclosure provide an apparatus for wireless communication. The apparatus includes a transceiver and a processing circuit. The transceiver is configured to transmit and receive wireless signals. The processing circuit is configured to detect an error of a previous scheduled transmission of data units from the apparatus to another apparatus. The other apparatus provides scheduled resources for transmission between the two apparatuses. Further, the processing circuit is configured to determine resources that are scheduled by the other apparatus for the apparatus to perform retransmission, and provide one or more of the data units in the previous scheduled transmission to the transceiver for retransmission using the scheduled resources.

Abstract: A wireless data communication radio includes a first transceiver configured to be coupled to a first antenna, and a second transceiver configured to be coupled to a second antenna. The second transceiver includes a multi-path detector. The wireless data communication radio transmits a radio signal via the first transceiver, receives the radio signal at the second transceiver, and determines, by the multi-path detector, that the radio signal, as received by the second transceiver, was transmitted by the first antenna and received by second antenna.

Abstract: A first communication device transmits a first physical layer protocol data units (PPDU) that includes a first null data packet announcement (NDPA) frame as part of a first ranging measurement exchange. The first communication device transmits a first null data packet (NDP) as part of the first ranging measurement exchange, and records a transmit time of the first NDP. The first communication device determines whether a second NDP was received correctly from a second communication device as part of the first ranging measurement exchange. In response to determining that the second NDP was not received correctly, the first communication device commences a second ranging measurement exchange, including transmitting a second PPDU that includes a second NDPA frame as part of the second ranging measurement exchange.

Abstract: A data processing system is implemented with a backup PCI Express system, which is able to take over as the primary PCI Express system for ensuring that an endpoint device continues to function in a desired manner when a root complex in the primary PCI Express system is no longer functioning correctly or is deactivated for maintenance. The endpoint device is coupled to the primary root complex and a backup root complex through a multiplexer. When a failure or shutdown of the primary root complex is detected, the multiplexer is signaled to switch the communication of data from occurring between the primary root complex and the endpoint device to then occur between the backup root complex and the endpoint device. A PCI Express Link may be utilized to communicate such a failure or shutdown and/or to transfer information from the primary PCI Express system to the backup PCI Express system when the switch occurs.

Abstract: A radio frequency (RF) front end receives one or more symbols of a first frame transmitted by a transmitter. The RF front end determines that the one or more received symbols are correlated to one or more address symbols, where the one or more address symbols are each a time-domain signal of subcarriers that the transmitter transmits. The RF front end provides the received one or more symbols to a baseband system based on the correlation. The baseband system recovers bits of a second frame within the first frame based on the received one or more symbols.

Abstract: Various embodiments relate to a cancellation circuit configured to generate a cancellation signal, including: an attenuator configured to attenuate a transmitted signal from an aggressor transmitter based upon a first attenuation value; an I/Q demodulator configured to split an attenuated signal into in-phase (I) and quadrature signals (Q); a phase interpolator configured to apply a calibration phase shift and a calibration attenuation to the I signal and Q signal and to recombine the I and Q signals; an auxiliary balun coupled to an output of the phase interpolator; and an auxiliary power amplifier with an input connected to the auxiliary balun configured to generate the cancellation signal, wherein the output of the auxiliary power amplifier is connected to an output of a victim transmitter.

Abstract: A low power comparator circuit is provided. The circuit includes a comparator core including a first stage. The first stage has an output configured to provide a digital value. A capacitor includes a first terminal coupled at an input of the first stage and a second terminal selectively coupled to a first input and a second input of the comparator core. A voltage generator is coupled to the first stage. The voltage generator is configured and arranged to generate a first voltage based on a predetermined input current and to limit a maximum current of the first stage based on the predetermined input current.

Abstract: Aspects of the present disclosure are directed to injection locking and related apparatuses. As may be implemented in accordance with one or more embodiments, an apparatus includes a plurality of injection-locking circuits configured to receive an injection signal, each injection-locking circuit including a mixer and a lock-detection circuit. In each of the injection-locking circuits, the lock-detection circuit detects a lock-status relationship between the injection signal and a signal output from the injection-locking circuit. In response to the lock-status relationship indicating an unlocked condition, a phase/magnitude of the injection signal is adjusted. In response to the lock-status relationship indicating a locked condition, transmission of an FM continuous wave (FMCW) chirp signal is facilitated.

Abstract: A radar system utilizing a linear chirp that can achieve a larger MIMO virtual array than traditional systems is provided. Transmit channels transmit distinct chirp signals in an overlapped fashion such that the pulse repetition interval is kept short and the frame is kept short. This alleviates range migration and aids in achieving a high frame update rate. The chirp signals from differing transmitters can be separated on receive in the range spectrum domain, such that a MIMO virtual array construction is possible. Distinct chirps are delayed versions of the first chirp signal. Chirps overlap in the fast-time domain, but due to delay, there is separation in the range spectrum domain. When the delay is at least the instrument round-trip delay, transmitters are separable. Further, the wavelengths are identical across transmitters such that there is no residual-range versus angle ambiguity issue present in the claimed frequency-offset modulation range division MIMO system.

Abstract: A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.