Abstract: A panel carrier includes a substrate, a die-attach region, a short sidewall, and a conductor. The die-attach region is on a top substrate surface of the substrate for supporting the LCoS panel. The short sidewall is on a first side of the die-attach region and has a top sidewall surface at a first height above the top substrate surface exceeding 0.4 millimeters and an aperture spanning the top sidewall surface and the top substrate surface. The conductor at least partially fills the aperture for electrically connecting to the conductive layer. A method for mechanically and electrically connecting a LCoS panel to a panel carrier having a short sidewall includes electrically connecting a transparent conductive layer of the LCoS panel to a conductive material, within the short sidewall, with a conductive adhesive having a thickness, between the transparent conductive layer and the short sidewall, less than two-hundred micrometers.

Abstract: A notched-spacer camera module includes a chip-scale package, a lens plate, a spacer ring, and a glue ring. The chip-scale package has an image sensor and a top surface. The spacer ring includes a glue gate having a gate height and a spacer base, having a base height, between the glue gate and the lens plate. The glue ring is between the spacer ring and the top surface and has (i) an outer region between the top surface and a bottom surface of the spacer base, and (ii) an inner region, having an inner thickness, between the top surface and a bottom surface of the glue gate. The lens plate, the spacer ring, the glue ring, and the top surface form a sealed cavity having a cavity height equal to at least a sum of the inner thickness, the gate height, and the base height.

Abstract: A multi-color HDR image sensor includes at least a first combination color pixel with a first color filter and an adjacent second combination color pixel with a second color filter which is different from the first color filter, wherein each combination color pixel includes at least two sub-pixels having at least two adjacent photodiodes. Within each combination color pixel, there is a dielectric deep trench isolation (d-DTI) structure to isolate the two adjacent photodiodes of the two adjacent sub-pixels with same color filters in order to prevent the electrical cross talk. Between two adjacent combination color pixels with different color filters, there is a hybrid deep trench isolation (h-DTI) structure to isolate two adjacent photodiodes of two adjacent sub-pixels with different color filters in order to prevent both optical and electrical cross talk. Each combination color pixel is enclosed on all sides by the hybrid deep trench isolation (h-DTI) structure.

Abstract: An image sensor includes a substrate, a plurality of light sensitive pixels, a first plurality of color filters, a plurality of reflective sidewalls, and a second plurality of color filters. The light sensitive pixels are formed on said substrate. The first plurality of color filters is disposed over a first group of the light sensitive pixels. The reflective sidewalls are formed on each side of each of the first plurality of color filters. The second plurality of color filters are disposed over a second group of light sensitive pixels and each color filter of the second plurality of color filters is separated from each adjacent filter of said first plurality of color filters by one of the reflective sidewalls. In a particular embodiment an etch-resistant layer is disposed over the first plurality of color filters and the second group of light sensitive pixels.

Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.

Abstract: A photodiode is adapted to accumulate image charges. A transfer transistor transfers the image charges to the floating diffusion. A source follower transistor is coupled to receive the voltage of the floating diffusion and provide an amplified signal. A row select transistor enables the amplified signal and outputs the amplified signal to a bitline. A first current source generator is coupled between the bitline and a ground. The first current source generator sinks current through a first cascode transistor, a first bias transistor and a second bias transistor. The first cascode transistor is biased by a cascode control voltage. The first bias transistor and the second bias transistor are biased by a bias control voltage.

Abstract: A transmitter circuit coupled to output image data from an image sensor includes a plurality of transmitters. The transmitters may include a plurality of drivers coupled to receive a data signal, and output a differential signal in response to receiving the data signal. A de-emphasis circuit is coupled between a first output of a first driver in the plurality of drivers, and a second output of a second driver in the plurality of drivers. The de-emphasis circuit is coupled to receive a de-emphasis control signal, and in response to receiving the de-emphasis control signal, the de-emphasis circuit reduces a magnitude of the differential signal.

Abstract: A trenched device wafer includes a device substrate layer having a top surface; a plurality of devices in the device substrate layer, and a trench in the top surface. The trench extends into the device substrate layer, and is located between a pair of adjacent devices of the plurality of devices. A method for forming a device die from a device wafer includes forming a trench in a top surface of the device wafer between two adjacent devices of the device wafer. The trench has a bottom surface located (a) at a first depth beneath the top surface and (b) at a first height above a wafer bottom surface. The method also includes, after forming the trench, decreasing a thickness of the device wafer, between the two adjacent devices, to a thickness less than the first height.

Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges accumulated in the photodiode to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a SF gate terminal and provide an amplified signal to a source follower source terminal. A row select transistor is coupled to receive the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor controlled by a bitline enable voltage is coupled to link between the bitline and a bitline source node. The bitline is coupled to an idle voltage generator, a blacksun voltage generator, and a clamp voltage generator.

Abstract: Trenched-bonding-dam devices and corresponding methods of manufacture are provided. A trenched-bonding-dam device includes a bonding dam structure positioned upon a top surface of a substrate. The bonding dam structure has a bottom surface attached to a top surface of the substrate, an inner dam surrounded by an outer dam, and a trench between the inner and outer dams. The device may further include an optics system including a lens and an adhesive positioned within a bonding region between a bottom surface of the optics system and a top surface of at least one of the inner and outer dams. The trench may be dimensioned to receive a portion of the excess adhesive flowing laterally out of the bonding region during bonding of the substrate to the optics system, laterally confining the excess adhesive and reducing lateral bleeding of the adhesive.

Abstract: An imaging system includes a primary imager and plurality of 3A-control sensors. The primary imager has a first field of view and includes a primary image sensor and a primary imaging lens with a first optical axis. The primary image sensor has a primary pixel array and control circuitry communicatively coupled thereto. The plurality of 3A-control sensors includes at least one of a peripheral imager and a 3A-control sensor. The peripheral imager, if included, has a second field of view including (i) at least part of the first field of view and (ii) a phase-difference auto-focus (PDAF) sensor and a peripheral imaging lens, the PDAF sensor being separate from the primary image sensor. The 3A-control sensor, if included, is separate from the primary pixel array and communicatively connected to the control circuitry to provide one of auto-white balance and exposure control for the primary pixel array.

Abstract: A novel multi-display projection box includes a housing that is short and wide, a set of display panels, a set of projectors, and a controller. In a particular embodiment the set of display panels includes two display panels, each coupled to opposite sides of the housing. The set of projectors includes two projectors placed adjacent opposite side walls of the housing. One of the projectors projects a first image onto one of the display panels and the other projector projects a second image onto the other display panel. The first and second image can include product information corresponding to goods placed atop the projection box in a retail store.

Abstract: A photon detection device includes a single photon avalanche diode (SPAD) disposed in a semiconductor layer. A guard ring structure is disposed in the semiconductor layer surrounding the SPAD to isolate the SPAD. A well region is disposed in the semiconductor layer surrounding the guard ring structure and disposed along an outside perimeter of the photon detection device. A contact region is disposed in the well region only in a corner region of the outside perimeter such that there is no contact region disposed along side regions of the outside perimeter. A distance between an inside edge of the guard ring structure and the contact region in the corner region of the outside perimeter is greater than a distance between the inside edge of the guard ring structure and the side regions of the outside perimeter such that an electric field distribution is uniform around the photon detection device.

Abstract: An image sensor includes a semiconductor material having a front side and a back side opposite the front side. The image sensor also includes a shallow trench isolation (STI) structure, an interlayer dielectric, an intermetal dielectric, and a contact area. The STI structure extends from the front side of the semiconductor material into the semiconductor material. The interlayer dielectric is disposed between the front side of the semiconductor material and the intermetal dielectric. The contact area is disposed proximate to a lateral edge of the semiconductor material. The contact area includes a metal interconnect disposed within the intermetal dielectric and a plurality of contact plugs at least partially disposed within the interlayer dielectric. The contact area also includes a contact pad. The plurality of contact plugs is coupled between the contact pad and the metal interconnect.

Abstract: An imaging system and method for generating a three-dimensional color image include an opening for allowing light from an object to enter the imaging system. Each sensor element in an array of sensor elements receives a portion of the light and generates a signal indicative of an intensity of the received portion of the light. Light from an optical element impinges on a filter comprising a plurality of filter regions, each filter region passes a predetermined band of wavelengths of the light and is associated with and disposed in alignment with one of the sensor elements such that light passing through each filter region impinges on the sensor associated and in alignment with the filter element. At least one of the filter regions is constructed to pass a visible color band, and at least one other of the filter regions is constructed to pass an infrared band.

Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the transparent shield. The method further includes removing portions of the transparent shield to form recessed regions in the transparent shield, where lateral bounds of the transparent shield extend beyond lateral bounds of the pixel array, and wherein the recessed regions are disposed in portions of the transparent shield that extend beyond the lateral bounds of the pixel array. The recessed regions are filled with a light blocking layer.

Abstract: A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure.

Abstract: An imaging system includes a pixel array of pixel cells with each one of the pixel cells including a photodiode disposed in a semiconductor material, a global shutter gate transistor, disposed in the semiconductor material and coupled to the photodiode, a storage transistor disposed in the semiconductor material, an optical isolation structure disposed in the semiconductor material to isolate a sidewall of the storage transistor from stray light and stray charge. The optical isolation structure also includes a deep trench isolation structure that is filled with tungsten and a P+ passivation formed over an interior sidewall of the deep trench optical isolation structure. Each one of the pixel cells also include control circuitry coupled to the pixel array to control operation of the pixel array and readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.

Abstract: A CMOS photodiode device for use in a dual-sensitivity imaging pixel contains at least two areas of differential doping. Transistors are provided in electrical contact with these areas to govern operation of signals emanating from the photodiode on two channels, each associated with a different sensitivity to light. A plurality of such photodiodes may be incorporate into a shared arrangement forming a single pixel, in order to enhance the signals.

Abstract: Apparatuses and methods for a skimming photodiode with high dynamic range (HDR) and reduced Light Emitting Diode (LED) flicker in imaging system are disclosed herein. A voltage generator provides a transfer gate voltage to a transfer transistor. The transfer gate voltage is a voltage selected one of a transfer-on, a transfer-off, and a skimming voltage. The transfer transistor transfers charges generated on a Complementary Metal-Oxide-Semiconductor (CMOS) photodiode (PD) to a floating diffusion (FD). The voltage on transfer gate controls the amount of the charges that can be transferred from the PD to the FD. A reset transistor precharges the PD and FD to an AVDD. A first enable transistor controls the amount of charges transferred from the FD to a first capacitor. A second enable transistor controls the amount of charges transferred from the FD to a second capacitor. The first and second enable transistors receive their individual periodical control pulses once activated.