Abstract: A novel image sensor includes error detection circuitry for detecting sequencing errors. In a particular embodiment a pattern is inserted into a captured image and an image processor detects sequencing errors by determining a location of the pattern. In a more particular embodiment, the image sensor includes a pixel array, arranged in columns and rows. A row select signal is encoded as a bitwise signal, and the bitwise signal is decoded by a multi-input AND gate associated with a particular column of the image sensor, based on a relationship between rows and columns of the pixel array. The relationship determines the pattern asserted into the captured image.

Abstract: A novel image sensor includes error detection circuitry for detecting sequencing errors. In a particular embodiment a pattern is inserted into a captured image and an image processor detects sequencing errors by determining a location of the pattern. In a more particular embodiment, the image sensor includes a pixel array, arranged in columns and rows. A row select signal is encoded as a bitwise signal, and the bitwise signal is decoded by a multi-input AND gate associated with a particular column of the image sensor, based on a relationship between rows and columns of the pixel array. The relationship determines the pattern asserted into the captured image.

Abstract: An image sensor comprises a semiconductor material having an illuminated surface and a non-illuminated surface; a photodiode formed in the semiconductor material extending from the illuminated surface to receive an incident light through the illuminated surface, wherein the received incident light generates charges in the photodiode; a transfer gate electrically coupled to the photodiode to transfer the generated charges from the photodiode in response to a transfer signal; a floating diffusion electrically coupled to the transfer gate to receive the transferred charges from the photodiode; a near infrared (NIR) quantum efficiency (QE) enhancement structure comprising at least two NIR QE enhancement elements within a region of the photodiode, wherein the NIR QE enhancement structure is configured to modify the incident light at the illuminated surface of the semiconductor material by at least one of diffraction, deflection and reflection, to redistribute the incident light within the photodiode to improve an

Abstract: An image sensor includes a semiconductor material including a photodiode disposed in the semiconductor material and an insulating material. A surface of the semiconductor material is disposed between the insulating material and the photodiode. The image sensor also includes isolation structures disposed in the semiconductor material and in the insulating material, and the isolation structures extend from within the semiconductor material through the surface and into the insulating material. The isolation structures include a core material and a liner material. The liner material is disposed between the core material and the semiconductor material, and is also disposed between the insulating material and the core material.

Abstract: An image sensor includes a substrate, a first set of sensor pixels formed on the substrate, and a second set of sensor pixels formed on the substrate. The sensor pixels of the first set are arranged in rows and columns and are configured to detect light within a first range of wavelengths (e.g., white light). The sensor pixels of the second set are arranged in rows and columns and are each configured to detect light within one of a set of ranges of wavelengths (e.g., red, green, and blue). Each range of wavelengths of the set of ranges of wavelengths is a subrange of said first range of wavelengths, and each pixel of the second set of pixels is smaller than each pixel of the first set of pixels.

Abstract: A liquid crystal display includes a display area and a border area at least partially surrounding the display area, where the display area displays images for viewing and the border area displays display-protection images, which are used to control ion migration in the liquid crystal layer. In a more particular embodiment, the border area displays a series of checkerboard pattern(s), where the checkerboard patterns can alternate between initial and inverted values. The display-protection images protect the liquid crystal display from migrating ions accumulating in particular regions of the pixel array and causing permanent defects in the display area. A liquid crystal display that includes a liquid crystal alignment layer having a plurality of liquid crystal alignment directions is also disclosed. The customized liquid crystal alignment director(s) over the border area promote ion migration away from the display area.

Abstract: A liquid crystal display includes a display area and a border area at least partially surrounding the display area, where the display area displays images for viewing and the border area displays display-protection images, which are used to control ion migration in the liquid crystal layer. In a more particular embodiment, the border area displays a series of checkerboard pattern(s), where the checkerboard patterns can alternate between initial and inverted values. The display-protection images protect the liquid crystal display from migrating ions accumulating in particular regions of the pixel array and causing permanent defects in the display area. A liquid crystal display that includes a liquid crystal alignment layer having a plurality of liquid crystal alignment directions is also disclosed. The customized liquid crystal alignment director(s) over the border area promote ion migration away from the display area.

Abstract: A method of image sensor fabrication includes forming a photodiode and a floating diffusion in a first semiconductor material, and removing part of an oxide layer disposed proximate to a seed area on a surface of the first semiconductor material. The method also includes depositing a second semiconductor material over the surface of the first semiconductor material, and annealing the first semiconductor material and second semiconductor material. A portion of the second semiconductor material is etched away to form part of a source follower transistor, and dopant is implanted into the second semiconductor material to form a first doped region, a third doped region, and a second doped region. The second doped region is laterally disposed between the first doped region and the third doped region, and the second doped region is a channel of the source follower transistor.

Abstract: Example comparators as disclosed herein may include a first comparator comprising a first plurality of device areas, wherein the first plurality of device areas at least includes a first comparator input device area, a first comparator cascode device area, and a first comparator current mirror area, and a second comparator comprising a second plurality of device areas, wherein the second plurality of device areas at least includes a second comparator input device area, a second comparator cascode device area, and a second comparator current mirror area, where the second comparator input area is disposed between the first comparator input area and the first comparator cascode device area, the first comparator cascode device area is disposed between the second comparator input area and the second comparator cascode device area, the first comparator current mirror area is disposed between the first comparator cascode device area and the second comparator current mirror area, the second comparator cascode device

Abstract: An image sensor includes first and second pluralities of photodiodes interspersed among each other in a semiconductor substrate. Incident light is to be directed through a surface of the semiconductor substrate into the first and second pluralities of photodiodes. The first plurality of photodiodes has greater sensitivity to the incident light than the second plurality of photodiodes. A metal film layer is disposed over the surface of the semiconductor substrate over the second plurality of photodiodes and not over the first plurality of photodiodes. A metal grid is disposed over the surface of the semiconductor substrate, and includes a first plurality of openings through which the incident light is directed into the first plurality of photodiodes. The metal grid further includes a second plurality of openings through which the incident light is directed through the metal film layer into the second plurality of photodiodes.

Abstract: An image sensor package includes an image sensor with a pixel array disposed in a semiconductor material. A first transparent shield is adhered to the semiconductor material, and the pixel array is disposed between the semiconductor material and the first transparent shield. The image sensor package further includes a second transparent shield, where the first transparent shield is disposed between the pixel array and the second transparent shield. A light blocking layer is disposed between the first transparent shield and the second transparent shield, and the light blocking layer is disposed to prevent light from reflecting off edges of the first transparent shield into the pixel array.

Abstract: A pixel circuit for use in an image sensor includes an unpinned photodiode disposed in a semiconductor material. The unpinned photodiode adapted to photogenerate charge carriers in response to incident light. A floating diffusion is disposed in the semiconductor and coupled to receive the charge carriers photogenerated in the unpinned photodiode. A transfer transistor is disposed in the semiconductor material and coupled between the unpinned photodiode and the floating diffusion. The transfer transistor is adapted to be switched on to transfer the charge carriers photogenerated in the unpinned photodiode to the floating diffusion. A boost capacitor is disposed over a surface of the semiconductor material proximate to the unpinned photodiode. The boost capacitor is coupled to receive a photodiode boost signal while the transfer transistor is switched on to further drive the charge carriers photogenerated in the unpinned photodiode to the floating diffusion.

Abstract: A pixel circuit includes a photodiode, and a transfer transistor coupled to the photodiode. A floating diffusion is coupled to the transfer transistor coupled to transfer image charge from the photodiode to the floating diffusion. An amplifier circuit includes an input coupled to the floating diffusion, an output coupled to generate an image data signal of the pixel circuit, and a variable bias terminal coupled to receive a variable bias signal. A reset switch is coupled between the output and input of the amplifier circuit to reset the amplifier circuit in response to a reset signal. A variable bias generator circuit is coupled to generate the variable bias signal in response to a reset signal to transition the variable bias signal from a first bias signal value to a second bias signal value in response to a transition of the reset signal from an active state to an inactive state.

Abstract: A pixel circuit includes a transfer transistor coupled between a photodiode and a floating diffusion to selectively transfer image charge accumulated in the photodiode to the floating diffusion. A selection circuit is coupled to select one of a first transfer control signal, a second transfer control signal, or a third transfer control signal to control the transfer transistor. The selection circuit is coupled to output the first transfer control signal in response to a precharge enable signal during a read out operation of a different row than a row in which the transfer transistor is included, to output the second transfer control signal in response to a sample enable signal during a read out operation of the row in which the transfer transistor is included, and output the third transfer control signal to partially turn on the transfer transistor during an idle state of the pixel circuit.

Abstract: An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.

Abstract: A highly-reflective liquid crystal on silicon (LCOS) panel includes pixel electrodes on a substrate, each pixel electrode having a top surface with a first reflectivity. A continuous reflective coating covers the pixel electrodes and substrate surfaces therebetween, forming a plurality of coated pixel electrodes having an enhanced reflectivity that exceeds the first reflectivity. A method for increasing pixel reflectivity in a LCOS panel includes depositing a continuous reflective coating covering both (1) a plurality of pixel electrodes on a substrate and (2) a plurality of inter-pixel substrate surfaces, and depositing a layer on the continuous reflective coating.

Abstract: A near-eye display device, with coaxial eye imaging, for mounting in field of view of an eye of a user, includes a display unit for displaying a display image, a viewing unit for (i) presenting the display image to the eye based upon polarized visible light received from the display unit and (ii) transmitting ambient light from an ambient scene toward the eye, and an eye imaging unit including (a) an illumination module for generating infrared light, (b) a first polarizing beamsplitter interface, disposed between the display unit and the viewing unit, for (i) merging a polarized infrared component of the infrared light with the polarized visible light and (ii) separating from the polarized visible light a portion of the polarized infrared component reflected by the eye, and (c) a camera for forming an image of the eye based upon the polarized infrared component reflected by the eye.

Abstract: An alignment layer for a liquid crystal on silicon (LCOS) display includes a nano-particle layer. In a particular embodiment the nano-particle layer includes a lower nano-layer and an upper nano-layer, each formed onto oxide layers of the LCOS display. In a more particular embodiment, the lower nano-layer and the upper nano-layer are offset printed onto the oxide layers.

Abstract: A liquid crystal display device includes a first substrate, a pixel array formed on the first substrate, a transparent substrate, a liquid crystal layer disposed between the pixel array and the transparent substrate, a transparent electrode disposed between the transparent substrate and the liquid crystal layer, and an input electrode. The transparent electrode has a longer first edge and an orthogonal shorter second edge. The input electrode extends along, and is electrically coupled along, the first edge of the transparent electrode and has lower impedance than a portion of the transparent electrode overlying the pixel array. The input electrode can include additional portion(s) that extend along, and that are electrically-coupled along, the other edges of the transparent electrode. The input electrode reduces the common voltage propagation delay across the transparent electrode and improves reduces intensity variation over the display area, even for high-frequency common voltage waveforms.

Abstract: A pixel circuit includes a photodiode to accumulate image charge in response to incident light. A transfer transistor is disposed between the photodiode and a floating diffusion disposed in the first semiconductor layer to selectively transfer the image charge accumulated in the photodiode to the floating diffusion. A select circuit is disposed in second semiconductor layer coupled to a control terminal of the transfer transistor through a hybrid bond between the first and second semiconductor layers to select between first and second transfer control signals to control the transfer transistor. The select circuit is coupled to output the first transfer control signal in response to a precharge enable signal during a read out operation of a different row, and output the second transfer control signal in response to a sample enable signal during a read out operation of the row.