Abstract: An image sensor includes a substrate, a first set of sensor pixels formed on the substrate, and a second set of sensor pixels formed on the substrate. The sensor pixels of the first set are arranged in rows and columns and are configured to detect light within a first range of wavelengths (e.g., white light). The sensor pixels of the second set are arranged in rows and columns and are each configured to detect light within one of a set of ranges of wavelengths (e.g., red, green, and blue). Each range of wavelengths of the set of ranges of wavelengths is a subrange of said first range of wavelengths, and each pixel of the second set of pixels is smaller than each pixel of the first set of pixels.

Abstract: An image sensor includes a substrate and a plurality of infrared pixels formed in a front side of the substrate and configured to detect infrared light incident on the front side of the substrate. Each of the infrared pixels includes a photodiode, a region free of implants located above the photodiode, and a photogate formed over the substrate and above the photodiode. The image sensor also includes a plurality of color pixels dispersed among the infrared pixels, where each of the color pixels includes a pinned photodiode and is configured to detect visible light. The photodiode of each of the infrared pixels can include a deep charge-accumulation region underlying the pinned photodiode(s) of one or more neighboring color pixel(s). Methods of manufacturing also described and include forming the deep charge-accumulation regions and associated elements prior to forming any implant-blocking elements (e.g., polysilicon photogates) over the substrate.

Abstract: An image sensor pixel includes a photodiode region formed in a semiconductor layer, a pinning layer and a depletion adjustment layer. The photodiode region receives visible and infrared light from a light incident side of the image sensor pixel. The pinning layer is disposed between a front surface of the semiconductor layer and the photodiode region, while the depletion adjustment layer is disposed between the pinning layer and the photodiode region. The depletion adjustment layer is configured to adjust a depletion region of the photodiode region to reduce charge carriers induced in the photodiode region by the received infrared light.

Abstract: An image sensor includes a photodiode disposed in a first semiconductor material, and the photodiode is positioned to absorb image light through the backside of the first semiconductor material. A first floating diffusion is disposed proximate to the photodiode and coupled to receive image charge from the photodiode in response to a transfer signal applied to a transfer gate disposed between the photodiode and the first floating diffusion. A second semiconductor material, including a second floating diffusion, is disposed proximate to the frontside of the first semiconductor material. A dielectric material is disposed between the first semiconductor material and the second semiconductor material, and includes a first bonding via extending from the first floating diffusion to the second floating diffusion, a second bonding via disposed laterally proximate to the first bonding via, and a third bonding via disposed laterally proximate to the first bonding via.

Abstract: A backside illuminated image sensor includes a semiconductor material with a plurality of photodiodes disposed in the semiconductor material, and a transfer gate electrically coupled to a photodiode in the plurality of photodiodes to extract image charge from the photodiode. The image sensor also includes a storage gate electrically coupled to the transfer gate to receive the image charge from the transfer gate. The storage gate has a gate electrode disposed proximate to a frontside of the semiconductor material, an optical shield disposed in the semiconductor material, and a storage node disposed between the gate electrode and the optical shield. The optical shield is optically aligned with the storage node to prevent the image light incident on the backside illuminated image sensor from reaching the storage node.

Abstract: A wafer-level liquid-crystal-on-silicon (LCOS) projection assembly includes a LCOS display for spatially modulating light incident on the LCOS display and a polarizing beam-separating (PBS) layer for directing light to and from the LCOS display. A method for fabricating a LCOS projection system includes disposing a PBS wafer above an active-matrix wafer. The active-matrix wafer includes a plurality of active matrices for addressing liquid crystal display pixels. The method, further includes disposing a lens wafer above the PBS wafer. The lens wafer includes a plurality of lenses. Additionally, a method for fabricating a wafer-level polarizing beam includes bonding a PBS wafer and at least one other wafer to form a stacked wafer. The PBS wafer includes a PBS layer that contains a plurality of PBS film bands.

Abstract: Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.

Abstract: A readout circuit for use in an image sensor includes a system ramp generator coupled to generate a system ramp signal. A plurality of analog-to-digital converters is coupled to a plurality of column bitlines from a pixel array to receive corresponding analog column image signals. An isolation ramp buffer is coupled between the system ramp generator and the analog-to-digital converters. The isolation ramp buffer includes a single input to receive the system ramp signal, and a plurality of isolated outputs. Each of the isolated outputs is coupled to provide an isolated column ramp signal to a corresponding analog-to-digital converter. Each of the of analog-to-digital converters is coupled to generate a corresponding digital column image signal in response to the corresponding analog column image signal and corresponding isolated column ramp signal.

Abstract: A system for evaluating a classifier of an image signal processor (ISP) includes (i) a microprocessor and (ii) memory storing training images, the microprocessor being capable of sending each training image to the ISP. The system includes machine-readable instructions stored within the memory and executed by the microprocessor capable of: (i) selecting a subset of images based upon a divider position, (ii) controlling the ISP to classify each image as belonging or not belonging to an object class, (iii) determining a positive-match count, (iv) determining an error count based upon the positive-match count and total number of training images belonging to the object class, (v) repeating, for other divider positions, steps of selecting, controlling, and determining to identify an optimal divider position and a minimum-error count; and (vi) determining the classifier's optimality by comparing the optimal divider position to a predetermined optimal divider position and a predetermined minimum-error count.

Abstract: An image sensor pixel having a hybrid transfer storage gate-storage diode storage node is disclosed herein. An example image sensor includes a photodiode, a storage diode, a transfer gate, and a buried storage well. The photodiode, storage diode, and buried storage well are all disposed in a semiconductor material. The transfer storage gate may be disposed on a surface of the semiconductor material between the photodiode and the storage diode. Further, the buried storage well may be disposed under the storage diode and partially under the transfer storage gate. Additionally, a length of the transfer storage gate and a length of the storage diode may be equal, and the storage diode may passivate a surface of the semiconductor material between the transfer storage gate and an output gate.

Abstract: An imaging system includes an image sensor and a row-period compensator. The image sensor includes an array of photosensitive pixels and electrical circuitry for controlling the array of photosensitive pixels and for reading accumulated electrical charge therefrom. The electrical circuitry is at least partially powered from a positive power rail and a negative power rail. The row-period compensator is for compensating for a change in current drawn by the electrical circuitry during at least part of a row-period of the image sensor, and the row-period compensator is electrically coupled between the positive and negative power rails. A method for compensating for a change in current drawn by electrical circuitry of an image sensor includes controlling a magnitude of compensation current drawn by a row-period compensator, to compensate for a change in current drawn by the electrical circuitry of the image sensor.

Abstract: A five-surface wide field-of view compound lens incudes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a first biplanar substrate, and a second biplanar substrate. The first lens is plano-concave; the second, the third lens, and the fourth lens are plano-convex; the fifth lens is a plano-gull-wing lens. The first biplanar substrate is between the second lens and the third lens. The second biplanar substrate is between the fourth lens and the fifth lens. The first lens has a first Abbe number. The second lens has a second Abbe number less than the first Abbe number. A camera module includes the five-surface wide FOV compound lens and a glass substrate having a planar surface adjoining a first planar surface of the first lens, the first lens being between the glass substrate and the second lens.

Abstract: A microscope attachment includes a lens apparatus with one or more lenses, a light source, and a sample holder. The sample holder is disposed between the lens apparatus and the light source and is positioned to transmit light from the light source through the sample holder and through the lens apparatus. The lens apparatus is disposed to enlarge an optical area in the sample holder. An attachment mechanism is disposed to connect the microscope attachment to a personal electronic device.

Abstract: A system for attaching a device to a glasses frame includes a spring clip that applies pressure to two sides of the glasses frame, and a magnet for attaching the device thereto. The device may attach directly to the magnet, or via a slide-on attachment piece. The spring clip may include a spring arm having distal ends that assist the spring clip in applying pressure to the glasses frames.

Abstract: A phase-detection auto-focus (PDAF) pixel array includes a first pixel and a second pixel. The first pixel, located at a first distance from a center of the PDAF pixel array, includes a first inner photodiode and a first outer photodiode with respect to the center. The first inner photodiode and the first outer photodiode occupy respectively a first inner area and a first outer area. The first inner area divided by the first outer area equals a first ratio. The second pixel, located at a second distance from the center that exceeds the first distance, includes a second inner photodiode and a second outer photodiode with respect to the center. The second inner photodiode and the second outer photodiode occupy respectively a second inner area and a second outer area. The second inner area divided by the second outer area equals a second ratio, which exceeds the first ratio.

Abstract: A pixel cell includes a photodiode disposed in a semiconductor material to accumulate image charge in response to light. A global shutter transistor is disposed in the semiconductor material and is selectively resets the image charge in the photodiode in response to a global shutter control signal. A global shutter control signal generator circuit is coupled to generate the global shutter control signal to have a first value, a second value, and a third value. The first value of the global shutter control signal is coupled to turn on the global shutter transistor to reset the photodiode. The third value of the global shutter control signal is coupled to control the global shutter transistor to be in a low leakage off mode. The second value of the global shutter control signal is between the first and third values and is turns off the global shutter transistor.

Abstract: A method for implementing H-Banding cancellation in an image sensor starts with a pixel array capturing image data. Pixel array includes a plurality of pixels to generate pixel data signals, respectively. ADC circuitry acquires the pixel data signals. ADC circuitry includes a comparator circuitry. In one embodiment, comparator circuitry 310 includes a plurality of comparators. Comparators included in comparator circuitry compare the pixel data signals, respectively, to a ramp signal received from a ramp generator to generate comparator output signals. Adjacent comparators output signals may be opposite in polarity. Other embodiments are described.

Abstract: Method of implementing stacked chip HDR algorithm in image sensor starts with pixel array capturing first frame with first exposure time and second frame with a second exposure time that is longer or shorter than the first exposure time. Pixel array is disposed in first semiconductor die and is partitioned into pixel sub-arrays. Each pixel sub-array is arranged into pixel groups, and each pixel group is arranged into pixel cell array. Readout circuits disposed in second semiconductor die acquire image data of first and second frame. Each pixel sub-array is coupled to a corresponding readout circuit through a corresponding one of a plurality of conductors. ADC circuits convert image data from first and second frames to first and second ADC outputs. Function logic on the second semiconductor die adding first and second ADC outputs to generate a final ADC output. Other embodiments are also described.

Abstract: A stacked image sensor includes a first plurality of photodiodes, including a first photodiode and a second photodiode, disposed in a first semiconductor material. A thickness of the first semiconductor material proximate to the first photodiode is less than the thickness of the first semiconductor material proximate to the second photodiode. A second plurality of photodiodes is disposed in a second semiconductor material. The second plurality of photodiodes is optically aligned with the first plurality of photodiodes. An interconnect layer is disposed between the first semiconductor material and the second semiconductor material. The interconnect layer includes an optical shield disposed between the second photodiode and a third photodiode included in the second plurality of photodiodes. The optical shield prevents a first portion of image light from reaching the third photodiode.

Abstract: A time of flight sensor includes control circuitry and a time of flight pixel array. The control circuitry is coupled to synchronously send a sync signal. The time of flight pixel array includes a plurality of time of flight pixel cells. Each one of the time of flight pixel cells includes a photosensor and a delay circuit. The photosensor is configured to generate an image signal in response to receiving photons from a light pulse reflected from an object. The delay circuit is coupled to generate a delayed sync signal in response to the sync signal. The delay circuit includes a delay transistor. The time of flight pixel array includes a transistor gradient where a transistor gate length of the delay transistor varies so that each of the time of flight pixel cells receive their respective delayed sync signal at a same time.