Abstract: An image sensor including a plurality of photodiodes disposed in a semiconductor layer and a plurality of deep trench isolation regions disposed in the semiconductor layer. The plurality of deep trench isolation regions include: (1) an oxide layer disposed on an inner surface of the plurality of deep trench isolation regions and (2) a conductive fill disposed in the plurality of deep trench isolation regions where the oxide layer is disposed between the semiconductor layer and the conductive fill. A plurality of pinning wells is also disposed in the semiconductor layer, and the plurality of pinning wells in combination with the plurality of deep trench isolation regions separate individual photodiodes in the plurality of photodiodes. A fixed charge layer is disposed on the semiconductor layer, and the plurality of deep trench isolation regions are disposed between the plurality of pinning wells and the fixed charge layer.

Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region.

Abstract: A system has in an integrated circuit a seed memory coupled to seed a vector generator that provides a vector to at least one scan chain of a first functional unit. A signature generator is configured to generate a signature from scan chain data, the signature is compared to an expected signature in a signature memory. A state memorizer is provided for saving a state of the functional unit and to restore the state of the functional unit as testing is completed. The system also has apparatus configured to determine an idle condition of the functional unit despite a non-idle state of the system; and a control unit configured to operate a test sequence when the functional unit is idle, the test sequence saving a state of the unit, generating vectors and signatures and verifying the signatures, and restoring the state of the unit.

Abstract: According to a picture-in-picture (PIP) system and method, a first image sensor device detects light from a first subject and generates a first signal indicative of image data for the first subject. A second image sensor device detects light from a second subject and generates a second signal indicative of image data for the second subject. Overlay logic combines the first and second signals to generate a picture-in-picture signal indicative of a combination of an image of the first subject and an image of the second subject, wherein the overlay logic is located within the first image sensor device. The first image sensor device generates a synchronization signal which is received by the second image sensor device and triggers the second image sensor device to generate the second signal indicative of image data for the second subject.

Abstract: Techniques and mechanisms for a pixel array to provide a level of conversion gain. In an embodiment, the pixel array includes conversion gain control circuitry to be selectively configured at different times for different operational modes, each mode for implementing a respective conversion gain. The conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—a supply voltage. In another embodiment, the conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—sample and hold circuitry.

Abstract: A method facilitating random access to segments of compressed data stored in memory includes the steps of receiving a series of data segments, encoding the series of data segments into a series of compressed data segments of variable segment sizes, storing the series of compressed data segments in a memory, and generating a locator for each of the compressed data segments. Each locator is indicative of the location of an associated compressed data segment in the memory. A method for randomly accessing a segment of compressed data includes receiving a request for a compressed data segment, retrieving a locator associated with the requested segment, using the retrieved locator to locate the requested segment in the memory, and retrieving the requested segment from the memory. Thus, compressed data segments can be decoded in a different order than the order they were encoded in. Systems for implementing the methods are also disclosed.

Abstract: An imaging device provides efficient heat transfer by orienting components of the imaging device such that heat is transferred out of the imaging device instead of within the imaging device assembly. Heat is transferred out of the imaging device assembly through a printed circuit board to which the assembly housing is mounted thereon and/or through the housing itself.

Abstract: A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.

Abstract: An image sensor pixel for use in a high dynamic range image sensor includes a first photodiode and a second photodiode. The first photodiode include a first doped region, a first lightly doped region, and a first highly doped region disposed between the first doped region and the first lightly doped region. The second photodiode disposed in has a second full well capacity substantially equal to a first full well capacity of the first photodiode. The second photodiode includes a second doped region, a second lightly doped region, and a second highly doped region disposed between the second doped region and the second lightly doped region. The first photodiode can be used to for measuring low light and the second photodiode can be used for measuring bright light.

Abstract: An example bandgap reference circuit includes an amplifier, a first, a second, and a third switch, and a capacitor. The first switch is coupled between an inverting input and an output of the amplifier to provide a negative feedback loop around the amplifier when the first switch is closed. The capacitor has a first end coupled to the inverting input, and a second end coupled to the second switch, where the capacitor is charged to a voltage substantially equal to an offset voltage of the amplifier when the second switch is closed. The third switch is coupled to a second end of the capacitor, where the voltage across the capacitor is subtracted from an input loop of the reference circuit to cancel the offset voltage of the amplifier when the third switch is closed.

Abstract: An image sensor for capturing both visible light images and infrared light images includes a semiconductor substrate having length, width, and height, a plurality of visible light photodetectors disposed in the semiconductor substrate, and a plurality of combination light photodetectors disposed in the semiconductor substrate. Each of the plurality of visible light photodetectors has a respective depth in the height direction, and each of the plurality of combination light photodetectors has a respective depth in the height direction that is greater than the respective depth of each of the plurality of visible light photodetectors.

Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

Abstract: An image data aggregating high dynamic range imaging system includes an image sensor for generating N image data sets from an array of photodiodes, where N is an integer greater than one. The image sensor is adapted to generate each of the N image data sets with a different respective exposure time duration of the array of photodiodes. The system further includes an image data aggregating module for aggregating the N image data sets to obtain a virtual long exposure image data set.

Abstract: An image sensor includes a pixel array including a plurality of pixel cells each including a floating diffusion node, a photosensitive element coupled to selectively transfer image charge to the floating diffusion node, and a feedback coupling capacitor coupled between the floating diffusion node and an output line. A bit line is coupled to selectively readout image data output from each one of a group of the plurality of pixel cells. An integrator is capacitively coupled to the bit line. The integrator is coupled to output an output signal on the output line in response to the image data. The output signal on the output line is capacitively coupled to the floating diffusion node through the feedback coupling capacitor to suppress a potential swing at the floating diffusion node of each one of the group of the plurality of pixel cells in response to the output signal.

Abstract: A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively.

Abstract: A thermal carrier and method control a temperature of an LCOS display panel. The temperature of the LCOS display panel is determined Electrical power to a heating element within a thermal carrier carrying the LCOS display panel is increased when the temperature of the LCOS display panel is below a first temperature threshold and electrical power to the heating element is decreased when the temperature of the LCOS display panel is above a second temperature threshold.

Abstract: An optical system has a first relief-type diffraction grating fiducial, or alignment mark, on a transparent surface of a first optical wafer or plate, the grating arranged to deflect light away from an optical path and appear black. The first wafer may have lenses. The first fiducial is aligned to another fiducial on a second wafer having further optical devices as part of system assembly; or the fiducials are aligned to alignment marks or fiducials on an underlying photosensor. Once the optical devices are aligned and the wafers bonded, they are diced to provide aligned optical structures for a completed camera system. Alternatively, an optical wafer is made by aligning a second relief-type diffraction grating fiducial on a first master to a first relief-type diffraction grating fiducial on an optical wafer preform, pressing the first master into a blob to form optical shapes and adhere the blob to the optical wafer preform.

Abstract: A CMOS imaging system is capable of self-calibrating to correct for lens shading by use of images captured in the normal environment of use, apart from a production calibration facility.

Abstract: A dual pixel-size color image sensor, including an imaging surface, for imaging of incident light, and a plurality of color pixels, each color pixel including (a) four large photosites, including two large first-color photosites sensitive to a first color of the incident light, and (b) four small photosites including two small first-color photosites sensitive to the first color of the incident light. The large and small first-color photosites are arranged such that connected regions of the imaging surface, not associated with large and/or small first-color photosites, are not continuous straight lines. A method for manufacturing a color filter array on an imaging surface of a dual pixel-size image sensor includes forming a first-color coating on first portions of the imaging surface to form large and small first-color photosites sensitive to a first color, wherein connected portions of the imaging surface, different from the first portions, are not continuous straight lines.

Abstract: A housing for protecting a wafer-level camera module and fixing the wafer-level camera module to a printed circuit board (PCB) includes: four side plates, defining a quadrilateral frame; four supporting plates each fixed to a lower portion of an inner face of a corresponding one of the four side plates, each supporting plate having a top face supporting a portion of the camera module; and four bottom plates each fixed to a lower portion of an outer face of a corresponding one of the four side plates, each bottom plate having a bottom face fixed to the PCB. The housing is capable of addressing the issues of poor housing-PCB soldering, paint falling off and surface scratching and improving the efficiency in UV lamp-utilized UV adhesive curing.