Abstract: A suspended lens system, for imaging a scene, includes (a) a single-piece lens for receiving light from the scene, wherein the single-piece lens includes a concave surface, and (b) a substrate including a side that faces the concave surface, for holding the single-piece lens, wherein the substrate has non-zero optical transmission and contacts only portions of the single-piece lens that are away from the concave surface. A wafer-level method for manufacturing a suspended lens system includes molding a lens array, wherein each lens of the lens array includes a concave surface, and bonding the lens array to a surface of a substrate that has non-zero optical transmission, such that the concave surfaces face the substrate, to form a suspended lens wafer.

Abstract: A wafer-level liquid-crystal-on-silicon (LCOS) projection assembly includes a LCOS display for spatially modulating light incident on the LCOS display and a polarizing beam-separating (PBS) layer for directing light to and from the LCOS display. A method for fabricating a LCOS projection system includes disposing a PBS wafer above an active-matrix wafer. The active-matrix wafer includes a plurality of active matrices for addressing liquid crystal display pixels. The method, further includes disposing a lens wafer above the PBS wafer. The lens wafer includes a plurality of lenses. Additionally, a method for fabricating a wafer-level polarizing beam includes bonding a PBS wafer and at least one other wafer to form a stacked wafer. The PBS wafer includes a PBS layer that contains a plurality of PBS film bands.

Abstract: Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node.

Abstract: A method for manufacturing a backside illuminated color image sensor includes (a) modifying the frontside of an image sensor wafer, having pixel arrays, to produce electrical connections to the pixel arrays, wherein the electrical connections extend depth-wise into the image sensor wafer from the frontside, and (b) modifying the backside of the image sensor wafer to expose the electrical connections.

Abstract: A thermal carrier and method control a temperature of an LCOS display panel. The temperature of the LCOS display panel is determined. Electrical power to a heating element within a thermal carrier carrying the LCOS display panel is increased when the temperature of the LCOS display panel is below a first temperature threshold and electrical power to the heating element is decreased when the temperature of the LCOS display panel is above a second temperature threshold.

Abstract: An image sensor includes a photosensing element for receiving infrared (IR) radiation and detecting the IR radiation and generating an electrical signal indicative of the IR radiation. A redistribution layer (RDL) is disposed under the photosensing element, the RDL comprising pattern of conductors for receiving the electrical signal. An IR reflection layer, an IR absorption layer or an isolation layer is disposed between the photosensing element and the RDL. The IR reflection layer, IR absorption layer or isolation layer provides a barrier to IR radiation such that the IR radiation does not impinge upon the RDL. As a result, a ghost image of the RDL is not generated, resulting in reduced noise and improved sensitivity and performance of the image sensor.

Abstract: A method for manufacturing a backside illuminated color image sensor includes (a) modifying the frontside of an image sensor wafer, having pixel arrays, to produce electrical connections to the pixel arrays, wherein the electrical connections extend depth-wise into the image sensor wafer from the frontside, and (b) modifying the backside of the image sensor wafer to expose the electrical connections.

Abstract: A method for black coating camera cubes at wafer level includes expanding the gap between individual diced camera cubes of the wafer by stretching tape securing the diced camera cubes. The method includes applying a black coating layer to the stretched camera cubes, laser trimming undesired portions of the black coating layer, and removing the undesired portions of the black coating layer.

Abstract: An optical zoom imaging system includes (1) first and second image sensors disposed on a common substrate, and (2) first and second optical blocks in optical communication with the first and second image sensors, respectively. The first and second optical blocks have different respective magnifications. An array includes a plurality of the optical zoom imaging systems. A method for imaging a scene includes the following steps: (1) generating first image data representing the scene at a first zoom level using a first optical block in optical communication with a first image sensor, (2) generating second image data representing the scene at a second zoom level using a second optical block in optical communication with a second image sensor, the second zoom level being different from the first zoom level, and (3) selecting between the first image data and the second image data based on a desired zoom level.

Abstract: A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and bonding the image sensor wafer to a lens wafer to form a composite wafer that includes the plurality of cameras. A wafer-level method for fabricating a plurality of cameras includes bonding an image sensor wafer to a lens wafer, using a pressure sensitive adhesive, to form a composite wafer that includes the plurality of cameras.

Abstract: An image sensor for three-dimensional (“3D”) imaging includes a first, a second, and a third pixel unit, where the second pixel unit is disposed between the first and third pixel units. Optical filters included in the pixel units are disposed on a light incident side of the image sensor to filter polarization-encoded light having a first polarization and a second polarization to photosensing regions of the pixel units. The first pixel unit includes a first optical filter having the first polarization, the second pixel unit includes a second optical filter having the second polarization, and the third pixel unit includes a third optical filter having the first polarization.

Abstract: A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element.

Abstract: An imaging system for use in a spatially constrained location includes an image sensor for capturing an image, wherein the image sensor has (a) a first rectangular area containing a pixel array and connecting circuitry communicatively coupled with the pixel array and (b) a second rectangular area with only one shared side with the first rectangular area and containing support electronics for pixel array control and signal acquisition, where the support electronics is communicatively coupled with the connecting circuitry. An imaging method for use in a spatially constrained location includes (a) forming an image of a scene on a pixel array of an image sensor contained within a first rectangular area having a first side and (b) communicating electrical signals between the pixel array and support electronics located onboard the image sensor and contained within a second rectangular area sharing only one side with the first rectangular area.

Abstract: An image data aggregating high dynamic range imaging system includes an image sensor for generating N image data sets from an array of photodiodes, where N is an integer greater than one. The image sensor is adapted to generate each of the N image data sets with a different respective exposure time duration of the array of photodiodes. The system further includes an image data aggregating module for aggregating the N image data sets to obtain a virtual long exposure image data set.

Abstract: Techniques and mechanisms for exchanging sets of video data each via multiple channels. In an embodiment, a first data set is distributed across the multiple channels according to a first mapping of the multiple channels each to a different respective one of multiple data types, where each of the multiple data types corresponds to a different respective dimension of a color space. In another embodiment, a second data set is distributed across the multiple channels according to a second mapping of the multiple channels each to a different respective one of the multiple data types, where the second mapping is different from the first mapping.

Abstract: An image sensor includes a first pixel unit horizontally adjacent to a second pixel unit. Each pixel unit includes plurality of photodiodes and a shared floating diffusion region. A first pixel transistor region of the first pixel unit has a plurality of pixel transistors. A second pixel transistor region of the second pixel unit is horizontally adjacent to the first pixel transistor region and also has a plurality of pixel transistors. A transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region.

Abstract: An apparatus of one aspect includes a photodetector array, and a peripheral region at a periphery of the photodetector array. A thinner interconnect line corresponding to the photodetector array is disposed within one or more insulating layers. A thicker interconnect line corresponding to the peripheral region is disposed within the one or more insulating layers. Other apparatus, methods, and systems are also disclosed.

Abstract: A photon detection device includes a photodiode having a planar junction disposed in a first region of semiconductor material. A deep trench isolation (DTI) structure is disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a dielectric layer lining an inside surface of the DTI structure and doped semiconductor material disposed over the dielectric layer inside the DTI structure. The doped semiconductor material disposed inside the DTI structure is coupled to a bias voltage to isolate the photodiode in the first region of the semiconductor material from the second region of the semiconductor material.

Abstract: An image sensor includes photosensitive regions, transfer transistors, and one or more shared charge-to-voltage mechanism. A method for reading out the image sensor includes enabling a first transfer transistor to transfer photo-generated charge from a first photosensitive region to a shared charge-to-voltage mechanism. The method also includes no more than partially enabling a second transfer transistor to partially turn on the second transfer transistor to increase a capacitance of the shared charge-to-voltage mechanism while the photo-generated charge is transferred from the first photosensitive region to the shared charge-to-voltage mechanism.

Abstract: A floorplan-optimized stacked image sensor and a method for designing the sensor are disclosed. A sensor layer includes multiple PSAs partitioned into PSA groups. A circuit layer includes multiple analog-to-digital converters each communicatively coupled to a different PSA. Each analog-to-digital converter (ADC) is semi-aligned to the PSA group associated with the PSA to which it is communicatively coupled. The floorplan of ADCs maximizes contiguous global-based space on the circuit layer uninterrupted by an ADC. The resulting circuit layer floorplan has one or more global-based spaces interleaved with one or more local-based spaces containing ADCs.