Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.
Type:
Application
Filed:
May 4, 2012
Publication date:
November 29, 2012
Applicant:
PMC-Sierra, Inc.
Inventors:
Peter Graumann, Sean Gibb, Stephen Bates
Abstract: Systems and methods for bandwidth doubling in an Ethernet passive optical network (EPON) enable an optical line terminal (OLT) to transmit downlink to at least one double rate optical network unit (ONU). The double rate transmission is preferably facilitated by use of single rate devices (OLT and ONU) functionally connected to provide the double rate capability. The methods include packet-by-packet multiplexing, bit-by-bit line code interleaving, doubling an inter-packet gap (IPG) length, defining windows of transmission for different transmission rates, using the 8B/10B code, removing the 8B/10B code from just the downlink transmission and symbol-by-symbol multiplexing is downlink transmissions from the double rate OLT.
Abstract: A method and protocol for dynamic upstream bandwidth allocation to prevent congestion in an aggregation system consisting of multiple PON OLT devices that share a common Service Network Interface (SNI). The method allows OLT devices to communicate real time user traffic load information, and for each OLT to self-throttle upstream throughput based on overall system view of traffic load. The method allows the available SNI bandwidth to be dynamically allocated to OLT ports while maintaining fairness per ONT (user). The method is implemented as a peer-to-peer protocol and does not require central controller resources. The method can be implemented in existing PON systems using software. The method saves the need for expensive dedicated traffic manager devices on the OLT aggregation point.
Abstract: Apparatus and methods apply pre-emphasis to the phase rather of a signal than to the amplitude of a single. This approach can provide superior pre-emphasis performance than the conventional amplitude pre-emphasis techniques in certain situations, such as when a non-linear slicer is present in the signal path. For example, electrical-to-optical (E/O) and optical-to-electrical (O/E) converters can effectively slice a signal.
Abstract: Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status to a DFE, and the DFE adjusts its filtering based on the provided information. The advantages are also applicable to fixed-gain amplifiers and to transversal filters.
Type:
Grant
Filed:
January 5, 2011
Date of Patent:
October 30, 2012
Assignee:
PMC-Sierra, Inc.
Inventors:
Matthew W. McAdam, Anthony Eugene Zortea
Abstract: A method and system are provided for controlling SAS/SATA disk spin up when a disk enters an inactive mode, such as standby mode, in a near line storage system. A routing table entry is modified for a selected hard disk drive in an expander routing table to redirect and reroute to a spinup control virtual target any access requests intended for the selected hard disk drive, in response to the selected hard disk drive being in standby mode. In response to the selected hard disk drive exiting standby mode, the routing table entry is modified to direct and route requests for access to the selected hard disk drive back to the drive itself. A SAS expander device can control spin up for standby disk drives in a disk array. Alternatively, spin up control can be performed for disks in other power modes, such as idle, in a disk array.
Abstract: A method for registration of multiple entities belonging to a specific optical network unit (ONU). In one embodiment, the multiple entity registration method comprises checking by an optical line terminal (OLT) if a registration request message received from the specific ONU belongs to a certain grant, and based on the check result, registering an entity as either a first or as an additional entity of the specific ONU. In another embodiment, the method comprises checking by an OLT of a reserved value of a flags field inside a registration request message, and based on the check result, registering an entity as either a first or as an additional entity of the specific ONU. The knowledge by an OLT that multiple entities belong to a specific ONU is used for grant optimization and packet data flow optimization.
Abstract: A system and method for power saving in IEEE 802-style and ITU-T G.984-style networks overcomes the limitations of conventional techniques using information from user and network devices for initiating power savings by the user or network device, enabling power savings on links such as optical networks. This innovative technique provides a system and method for communications between user and network devices, facilitating either the user or network device initiating a sleep mode for the user device. The implementation of a sleep mode in a device allows powering down of the device's transmitter and receiver for a specified length of time, during which the transmitter and receiver (also referred to as the physical interface of the device) consume diminished power.
Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.
Type:
Grant
Filed:
January 24, 2011
Date of Patent:
September 18, 2012
Assignee:
PMC-Sierra US, Inc.
Inventors:
Babysaroja Annem, David J. Clinton, Praveen Alexander
Abstract: A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.
Abstract: In a communication system in which data is transferred by packets, a ranging method in which a receiver, in a given ranging window, periodically compares received data with expected data to find a match. The periodic comparison includes searching for known preamble and/or delimiter sequences of ranging packets and involves timeouts for each search period. In case a match between the known sequences and received sequences is not found and the respective timeout is exceeded, the search and comparison process is restarted and continues until a global timeout is exceeded.
Abstract: Methods and apparatus are disclosed, such as those involving clock and data recovery sampler calibration. One such method includes receiving an electronic data stream by a clock and data recovery (CDR) circuit comprising a data sampler and an edge sampler. The data stream includes data portions and transitioning portions. The method further includes conducting calibration of the CDR circuit. The calibration includes acquiring samples from the transitioning portions of the data stream using the data sampler; and calibrating the data sampler based at least partially on the samples acquired using the data sampler. The method allows one not only to improve performance, but also to improve yield and reduce testing and screening requirements without requiring any additional circuitry to detect the offsets and works with regular input signals.
Abstract: Methods, systems, and computer programs for managing storage in a computer system using a solid state drive (SSD) read cache memory are presented. The method includes receiving a read request, which causes a miss in a cache memory. After the cache miss, the method determines whether the data to satisfy the read request is available in the SSD memory. If the data is in SSD memory, the read request is served from the SSD memory. Otherwise, SSD memory tracking logic is invoked and the read request is served from a hard disk drive (HDD). Additionally, the SSD memory tracking logic monitors access requests to pages in memory, and if a predefined criteria is met for a certain page in memory, then the page is loaded in the SSD. The use of the SSD as a read cache improves memory performance for random data reads.
Abstract: A method for registration of multiple entities belonging to a specific optical networks unit (ONU). In one embodiment, the multiple entity registration method comprises checking by an optical line terminal (OLT) if a registration request message (400) received from the specific ONU belongs to a certain grant (402), and based on the check result, registering an entity as either a first (408) or as an additional entity (404) of the specific ONU. In another embodiment, the method comprises checking by an OLT of a reserved value of a flags field (502) inside a registration request message (500), and based on the check result, registering an entity as either a first (508) or as an additional entity (504) of the specific ONU. The knowledge by an OLT that multiple entities belong to a specific ONU is used for grant optimization and packet data flow optimization.
Abstract: In a communication system in which data is transferred by packets, a ranging method in which a receiver, in a given ranging window, periodically compares received data with expected data to find a match. The periodic comparison includes searching for known preamble and/or delimiter sequences of ranging packets and involves timeouts for each search period. In case a match between the known sequences and received sequences is not found and the respective timeout is exceeded, the search and comparison process is restarted and continues until a global timeout is exceeded.
Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.
Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.
Abstract: Transceivers with multiple gain stages that include open loop and closed loop amplifiers are subject to differential non-linearity (DNL) errors in their total gain versus gain index curve due to the gain step variability of the open loop amplifiers. The initial and time varying DNL can be reduced by a control loop that uses the relative gain step precision of the closed loop amplifiers and of passive attenuators to establish a control loop to reduce the DNL of the total gain.
Abstract: In a passive optical network, dynamic bandwidth allocation and queue management methods and algorithms, designed to avoid fragmentation loss, guarantee that a length of a grant issued by an OLT will match precisely the count of bytes to be transmitted by an ONU. The methods include determining an ONU uplink transmission egress order based on a three-stage test, and various embodiments of methods for ONU report threshold setting.
Abstract: A system and method for providing redundant access paths to a storage device make use of a processor to analyze instructions received from hosts to allow for command queuing, host switching, and command replacement where necessary. The system allows for either Serially Attached SCSI or Serial ATA hard drives to be connected to the same topology and to require no host intervention on the coordination of drive access in a multi-host environment. A single ported SATA device can then appear multi-ported and can support a redundant architecture within a SAS topology.
Type:
Grant
Filed:
September 5, 2006
Date of Patent:
February 28, 2012
Assignee:
PMC-Sierra US, Inc.
Inventors:
Larrie Simon Carr, Heng Liao, Nicholas Kuefler, Keith Shaw