Patents Assigned to PMC-Sierra
  • Publication number: 20100272440
    Abstract: Systems and methods for bandwidth doubling in an Ethernet passive optical network (EPON) enable an optical line terminal (OLT) to transmit downlink to at least one double rate optical network unit (ONU). The double rate transmission is preferably facilitated by use of single rate devices (OLT and ONU) functionally connected to provide the double rate capability. The methods include packet-by-packet multiplexing, bit-by-bit line code interleaving, doubling an inter-packet gap (IPG) length, defining windows of transmission for different transmission rates, using the 8B/10B code, removing the 8B/10B code from just the downlink transmission and symbol-by-symbol multiplexing is downlink transmissions from the double rate OLT.
    Type: Application
    Filed: July 4, 2010
    Publication date: October 28, 2010
    Applicant: PMC SIERRA ISRAEL LTD.
    Inventors: Onn Haran, Ariel Maislos
  • Patent number: 7818648
    Abstract: A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a global error-counter, coupled to the OLT, for counting FEC-correctable errors, for each ONU, from a data stream from the GPON; and a CPU for extracting an ONU status, indicative of a faulty ONU, contingent on the errors from the global error-counter. A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a grant-start error-counter, coupled to the OLT, for counting grant-start errors, for each ONU, from a data stream from the GPON; a grant-end error-counter, coupled to the OLT, for counting grant-end errors for each ONU; and a CPU for extracting an ONU status, indicative of a faulty ONU, contingent on a parameter selected from the group consisting of the grant-start errors, the grant-end errors, and a combination thereof.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: October 19, 2010
    Assignee: PMC-Sierra Israel Ltd.
    Inventor: Onn Haran
  • Patent number: 7812693
    Abstract: The present invention provides a novel structure that can be used to make a common mode filter. Only the common mode will be attenuated and the differential mode will not be attenuated. This structure can be implemented in a number of ways, a specific embodiment using strip-line and slot-line junctions is very compact and well-suited to use with multilayer PCBs, and does not require any extra components. It can be designed to attenuate certain discrete frequencies, by designing the poles of the transfer function to be at these frequencies.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: October 12, 2010
    Assignee: PMC-Sierra US, Inc.
    Inventor: Predrag Acimovic
  • Patent number: 7802167
    Abstract: A system and method are provided to detect an extended error burst in a data interface. An original error burst has a given length prior to or during transmission. Data transmission processing can extend the original error burst beyond its original length to become an extended error burst with an effective length greater than the original error burst length. Such data transmission processing can include: de-interleaving data on a multi-lane data interface; feedback from a Decision Feedback Equalizer (DFE) receiver; and/or block line decoding, such as 8B/10B block line code decoding. An extended error burst detector can include a suitable error detecting code, such as an r-bit cyclic redundancy check (CRC) code developed in relation to known extended error burst patterns, to detect all extended error bursts based on an up to r-bit original error burst. The detector can also detect error bursts that are not extended beyond the original error burst length.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 21, 2010
    Assignee: PMC-Sierra US, Inc.
    Inventor: Steven Scott Gorshe
  • Patent number: 7788448
    Abstract: A cache system includes a cache memory dedicated to service a number of sequencers with sequencer code. A number of cache managers are defined to direct placement of sequencer code portions into the cache memory. Also, each of the number of cache managers is defined to provide sequencer code from the cache memory to a respectively assigned sequencer. An external memory is defined to store a complete version of the sequencer code. A direct memory access (DMA) engine is defined to write sequencer code portions from the external memory to the cache memory, in accordance with direction from the number of cache managers.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 31, 2010
    Assignee: PMC-Sierra US, Inc.
    Inventor: Marc Spitzer
  • Publication number: 20100208745
    Abstract: A method for registration of multiple entities belonging to a specific optical networks unit (ONU). In one embodiment, the multiple entity registration method comprises checking by an optical line terminal (OLT) if a registration request message (400) received from the specific ONU belongs to a certain grant (402), and based on the check result, registering an entity as either a first (408) or as an additional entity (404) of the specific ONU. In another embodiment, the method comprises checking by an OLT of a reserved value of a flags field (502) inside a registration request message (500), and based on the check result, registering an entity as either a first (508) or as an additional entity (504) of the specific ONU. The knowledge by an OLT that multiple entities belong to a specific ONU is used for grant optimization and packet data flow optimization.
    Type: Application
    Filed: February 23, 2010
    Publication date: August 19, 2010
    Applicant: PMC-SIERRA ISRAEL LTD.
    Inventors: Onn Haran, Ariel Maislos, Lior Khermosh
  • Patent number: 7777248
    Abstract: A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 17, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Graeme B. Boyd, Xun Cheng, Ariel D. E. Sibley
  • Patent number: 7778545
    Abstract: Systems and methods for bandwidth doubling in an Ethernet passive optical network (EPON) enable an optical line terminal (OLT) to transmit downlink to at least one double rate optical network unit (ONU). The double rate transmission is preferably facilitated by use of single rate devices (OLT and ONU) functionally connected to provide the double rate capability. The methods include packet-by-packet multiplexing, bit-by-bit line code interleaving, doubling an inter-packet gap (IPG) length, defining windows of transmission for different transmission rates, using the 8B/10B code, removing the 8B/10B code from just the downlink transmission and symbol-by-symbol multiplexing is downlink transmissions from the double rate OLT.
    Type: Grant
    Filed: October 2, 2005
    Date of Patent: August 17, 2010
    Assignee: PMC-Sierra Israel Ltd
    Inventors: Onn Haran, Ariel Maislos
  • Publication number: 20100201418
    Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Applicant: PMC-Sierra, Inc.
    Inventors: Jean-Francois Delage, Hormoz Djahanshahi, Guillaume Fortin
  • Patent number: 7774424
    Abstract: A method and apparatus for determining a set of common link rates for communication between two storage network elements in a storage network system. During the speed negotiation process, a controlling storage network element receives supported link rate information from a connected storage network element without providing any information in return. By not providing such information, although the speed negotiation process may not be completed, the controlling storage network element is still able to determine the supported link rates of the connected storage network element.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: August 10, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Patrick Neil Bailey, Larrie Simon Carr
  • Publication number: 20100183304
    Abstract: An OLT allocates a bandwidth budget and assigns upstream transmission order by receiving upstream transmission requests from a plurality of ONUs. Each ONU's request includes a requested guaranteed bandwidth and a requested best effort bandwidth. Each ONU has respective first and second attribute values. One attribute is given allocation priority over the other attribute. One attribute is given scheduling priority over the other attribute. Within each attribute, an allocation rank and a transmission rank is assigned to the possible attribute values. The bandwidth budget is allocated in accordance with the allocation priority and ranks. The upstream transmissions are scheduled in accordance with the scheduling priority and ranks.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 22, 2010
    Applicant: PMC SIERRA LTD.
    Inventor: Oren SPECTOR
  • Patent number: 7760122
    Abstract: An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the effective number of bits (ENOB) required from an ADC of a receiver can vary. The power consumption of certain ADC topologies, such as pipelined converter topologies, can vary with the number of bits. One embodiment dynamically varies the ENOB of an ADC to more optimally consume power. This can extend battery life.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: July 20, 2010
    Assignee: PMC-Sierra, Inc.
    Inventor: Anthony Eugene Zortea
  • Patent number: 7756197
    Abstract: A relatively high-speed serial data transmitter incorporates built in self test (BIST). The BIST circuit advantageously provides tests modes to obviate the need to build expensive test equipment for high-speed serial data devices, such as a serializer/deserializer (SerDes) or other transceivers. Multiple data paths in a finite impulse response (FIR) filter of transmitter of the SerDes or a transceiver can be independently tested. The transmitter output can also be selectively degraded to test a receiver of a transceiver. An attenuated output signal can be provided to test receiver sensitivity. A low-pass filter can be invoked to emulate a backplane, while a loopback circuit can provide the emulated backplane attenuation to the receiver to permit testing of the equalization circuitry of a receiver without requiring the presence of an actual backplane for testing.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: July 13, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Kenneth William Ferguson, Paul Laprise, Chris Siu
  • Publication number: 20100174901
    Abstract: A method and system is provided for securing communication on an EPON. Particularly different types of encrypted messages, each with a respective short MAC SegTAG, may be sent from the OLT to an ONU and from an ONU to the OLT without need for a full SecTAG with an explicit SCI. Discovery and control messages may be encrypted and a security offset may be less than 30 bytes. A packet header including its MAC address may be encrypted.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 8, 2010
    Applicant: PMC Sierra Ltd.
    Inventors: Lior KHERMOSH, Zachy Haramaty, Jeff Mandin
  • Patent number: 7751411
    Abstract: A method of interfacing for packet and cell transfer between a first layer device and a second layer device, which includes dividing control information into an in-band portion and an out-of-band portion, transmitting the in-band portion in the data path, and transmitting the out-of-band portion outside of the data path.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: July 6, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Richard Cam, James R. Hamstra, Winston Mok, David Wong
  • Patent number: 7747794
    Abstract: A method and apparatus are disclosed for implementing STP flow control in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. Connections to a SATA HDD are supported using SATA Tunnelling Protocol (STP), which allows SATA traffic to be carried over a SAS network topology. Flow control in a STP connection is applied through a set of special SATA primitives, both for forward and backward flow control. A method is described herein in which STP flow control is supported without the use of a SATA link layer state machine. This allows STP flow control to be terminated on a hop-by-hop basis without knowing the data channel direction or maintaining a SATA link state machine, and while minimizing gate count.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: June 29, 2010
    Assignee: PMC Sierra Ltd.
    Inventors: Paul Chong, Heng Liao, Cheng Yi
  • Patent number: 7743191
    Abstract: A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 22, 2010
    Assignee: PMC-Sierra, Inc.
    Inventor: Heng Liao
  • Patent number: 7739432
    Abstract: A multi-port switch and a method of command switching using such a switch. Multiple virtual targets provide multiple hosts with access to the physical target device attached to the target interface of the switch. The switch intelligently dispatches operations received by the virtual targets to the physical storage target device to provide shared access. In doing so, the communication between the switch and the physical target can fully comply with the SATA protocol without the physical target being aware that the operations have originated from multiple physical hosts, and without the multiple physical hosts being aware of the shared nature of the physical SATA target device.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: June 15, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Keith Shaw, Heng Liao, Larrie Simon Carr, Nicolas Kuefler
  • Patent number: 7738617
    Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: June 15, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Guillaume Fortin, Larrie Carr, Yuiry Greshishchev, Alex Cochran, Junqi (Paul) Hua
  • Publication number: 20100142975
    Abstract: A hybrid balanced code is formed from a low rate (narrow bandwidth) balanced code and a high rate (wide bandwidth) low density code. Data encoded using the hybrid balanced code is transmitted between a first communication network entity and a second communication network entity. The hybrid code enables a system having a hybrid transmitter to transmit either a low rate stream detectable by a low rate receiver or a hybrid stream, from which the low rate data may be detected by a low rate receiver while both the high rate data and the low rate data may be detected by a high rate receiver.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 10, 2010
    Applicant: PMC Sierra Ltd.
    Inventor: Raanan IVRY