Patents Assigned to PMC-Sierra
  • Patent number: 7936835
    Abstract: The adverse effects of RF and baseband circuits are mitigated using a post-compensation method wherein a transfer function that would un-distort or complement a distorted waveform is parameterized to a relatively small number of degrees of freedom; and the parameters are estimated in a feedback loop. The error function of the feedback loop is generated by comparing some relatively low-order statistics that are known a priori or can be computed with relative certainty from the decided output waveform—to the statistics of the corrected signal.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: May 3, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Anthony Eugene Zortea, Graeme Barclay Boyd
  • Patent number: 7936673
    Abstract: Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority traffic while capping maximum output rates for low priority traffic. By combining the two ideas of feedback rate control and placing maximum requestable transmission rates, a more equitable output sharing mechanism arises. The measured output transmission rate is used to control and recalculate the maximum requestable output transmission rate for incoming flows, thereby allowing for changing network and data flow conditions.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 3, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Shahram Davari, Heng Liao, Stacy William Nichols
  • Patent number: 7933276
    Abstract: A dynamic bandwidth allocation (DBA) processor comprises a DBA co-processor having DBA co-processor components and operative to perform and accelerate DBA functions, and a processing core logically coupled to the DBA co-processor through a processing bus and operative to configure and dynamically control all the DBA co-processor components and to run sections of algorithms that cannot be accelerated on the DBA co-processor. The DBA processor significantly accelerated the bandwidth allocation in a communications network such as an optical communications network or a fast wireless network. The DBA co-processor and the processing core may be integrated on a chip.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: April 26, 2011
    Assignee: PMC-Sierra Israel Ltd.
    Inventors: Onn Haran, Ariel Maislos
  • Patent number: 7920593
    Abstract: In a passive optical network, dynamic bandwidth allocation and queue management methods and algorithms, designed to avoid fragmentation loss, guarantee that a length of a grant issued by an OLT will match precisely the count for bytes to be transmitted to an ONU. The methods include determining an ONU uplink transmission egress based on a three-stage test, and various embodiments of methods for ONU report 700 threshold setting.
    Type: Grant
    Filed: March 30, 2008
    Date of Patent: April 5, 2011
    Assignee: PMC-Sierra Israel Ltd.
    Inventors: Onn Haran, Ariel Maislos, Barak Lifshitz
  • Patent number: 7916671
    Abstract: In a Frequency Duplex Division (FDD) radio, the transmit and receive signals are separated by frequency. In a wireless application, the power of the transmitted signal is typically much larger than the power of the received signal. A duplexer is used to separate the transmit and receive signals. Despite the operation of the duplexer, a residual transmit signal, or echo, can be present at the receiver input as a result of finite attenuation in the duplexer and other sources of transmit to receive crosstalk. With a relatively linear low-noise amplifier (LNA) and output limited mixer linearity, the echo can be cancelled in analog baseband directly at the mixer output using an out-of-channel signal indicator as the error signal for an echo control loop.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 29, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Anthony Eugene Zortea, Matthew McAdam
  • Patent number: 7912151
    Abstract: Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable gain amplifier (VGA), and can introduce significant nonlinearities, a problem exacerbated by signals with a large peak-to-average ratio (PAR). One embodiment provides feed forward information from the VGA regarding its status to a DFE, and the DFE adjusts its filtering based on the provided information. The advantages are also applicable to fixed-gain amplifiers and to transversal filters.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: March 22, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Matthew W. McAdam, Anthony Eugene Zortea
  • Patent number: 7913075
    Abstract: A method for provisioning a blade server is provided. The method includes creating a server boot image for a blade server, where the boot image includes an operating system image created from a donor server. Then, the method includes inserting the blade server into a chassis of an enclosure that is capable of receiving multiple blade servers. Then, staring the blade server from a pre-boot execution environment (PXE). The PXE loading an image that prompts a user to install a new operating system from a pre-existing target computer of the enclosure. The method then installs the new operating system. The installing includes creation of a new iSCSI target for the inserted blade server, and partitioning of the iSCSI target. The also includes restarting the inserted blade server. The restarting is configured to boot using the iSCSI target of the inserted blade server, so that the inserted blade server becomes a provisioned blade server.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: March 22, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Dean Kalman, Jeffrey MacFarland
  • Patent number: 7913151
    Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 22, 2011
    Assignee: PMC-Sierra, Inc.
    Inventor: Steven Scott Gorshe
  • Patent number: 7904033
    Abstract: The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a predistortion entity to provide a relatively constant gain. This attribute is advantageous for operation within cellular radio systems, which often employ digital power control systems. However, the disclosed techniques can also be applicable to virtually any type of digital predistortion for which an input signal or reference signal to be amplified is predistorted in a manner that is complementary to the distortion induced by a non-linear amplifier. Embodiments of the invention advantageously enhance the practicality of using digital linearization and predistortion amplification techniques.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 8, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Andrew S. Wright, Derek J. W. Ho, Bartholomeus T. W. Klijsen
  • Patent number: 7898295
    Abstract: Apparatus and methods provide low voltage differential signaling (LVDS) driver with replica circuit biasing and protection for hot plugging. The replica biasing is non-intrusive in nature, and can control the voltage swing tightly over parametric variations. The absence of an explicit near-end driver termination improves efficiency, while replica biasing controls output voltage swing levels. Hot-pluggable compatibility is achieved by a reduction in power-off leakage current and short circuit current protection.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: March 1, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Venkatesh Kasturirangan, Vikas Choudhary
  • Patent number: 7890840
    Abstract: The present invention discloses devices and methods for improving data correlation using a multiple-correlation state-machine, the method including the steps of: (a) pre-processing a data frame having a plurality of symbol sets, wherein each symbol set demarks a respective frame field of the frame, to provide a threshold-compared hamming-distance indicator; (b) comparing the threshold-compared hamming-distance indicator with at least one multiple-correlation threshold to provide a threshold-compared multiple-correlation indicator; and (c) combining the threshold-compared hamming-distance indicator and the threshold-compared multiple-correlation indicator to determine a match/no-match comparison indicative of the respective frame field. In some embodiments, the step of combining includes forming a logical-AND of the threshold-compared hamming-distance indicator and the threshold-compared multiple-correlation indicator.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: February 15, 2011
    Assignee: PMC-Sierra Israel Ltd.
    Inventors: Lior Khermosh, Onn Haran
  • Patent number: 7884660
    Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: February 8, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Jean-Francois Delage, Hormoz Djahanshahi, Guillaume Fortin
  • Patent number: 7877581
    Abstract: A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 25, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Shridhar Mukund, Mahesh Gopalan, Neeraj Kashalkar
  • Patent number: 7877524
    Abstract: A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: January 25, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Babysaroja Annem, Heng Liao, Zhongzhi Liu, Praveen Alexander
  • Patent number: 7876866
    Abstract: A method and apparatus are provided for reducing, and preferably substantially eliminating, data-pattern autocorrelations found in digital communication systems. The method employed is referred to as Data Subset Selection (DSS) and is implemented in the form of DSS engine. Autocorrelations in the data-pattern can cause many digital adaptive systems to converge to an incorrect solution. For example, the LMS method, which is often used in adaptive filtering applications, can converge to an incorrect set of filter coefficients in the presence of data-pattern autocorrelations. Digital timing recovery methods are also susceptible. Other impairments that result from data-pattern autocorrelations include increased convergence time and increased steady-state chatter.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: January 25, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventors: Matthew W. McAdam, Jurgen Hissen, Graeme Boyd
  • Patent number: 7860941
    Abstract: In one of many embodiments, an InfiniBand network architecture is provided where a router circuitry communicates data between a host and a target device where the router circuitry includes circuitry for generating an external queue pair (QP) for establishing communication between the router circuitry and the host through a reliable connection (RC) session. The router circuitry also includes circuitry for generating internal queue pairs where the internal queue pairs establishes communication between the router circuitry and a device controller, between the between the device controller and the target device, and between the router circuitry and the target device by using reliable connection (RC) sessions. The router circuitry also includes mapping circuitry capable of establishing data destinations in communications between the target and the host. The internal queue pairs are coupled with the external queue pair through the mapping circuitry.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: December 28, 2010
    Assignee: PMC-Sierra US, Inc.
    Inventor: Andrew W. Wilson
  • Patent number: 7860103
    Abstract: Methods and apparatus for increasing the number of addressable node ports within one arbitrated loop are provided in a way that allows all node ports be able to participate in loop operations. The method also adds destination filtering based on the source address to determine which of the similarly addressed node ports a message is destined for. A unique arbitrated loop physical address is acquired by a connectivity device. A shared arbitrated loop physical address is acquired by each drive in a set of drives attached to the connectivity device. The shared arbitrated loop physical address is part of a set of shared arbitrated loop physical addresses that are shared among a plurality of connectivity devices. The drive can be uniquely addressed using a pairing of the shared loop physical address associated with the drive and the unique arbitrated loop physical address associated with the selected connectivity device.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: December 28, 2010
    Assignee: PMC-Sierra US, Inc.
    Inventor: April I. Bergstrom
  • Publication number: 20100303093
    Abstract: Methods for increasing upstream bandwidth utilization in an Ethernet passive optical network (EPON) use in some instances round-down instead of round-up occupancy values reported to an optical line terminal. An optical network unit determines whether the occupancy needs to be round-up or round-down and reports the occupancy in either round-up or round-down report units to the optical network terminal.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 2, 2010
    Applicant: PMC Sierra Ltd.
    Inventors: Zachy Haramaty, Jeff Mandin, Valentin Ossman
  • Patent number: 7844650
    Abstract: A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency fref. The clock signal generator generates an output clock signal having a frequency fgen, wherein fgen is less than fref. A modulo-N counter accepts the reference clock signal as input. The modulo-N counter generates a phase-indication signal of the reference clock. The phase indication signal has N clock phases repeating at a frequency of fref/N. An accumulator iteratively accumulates a frequency control word into a modulo-N adder and produces an accumulated value. One or more bits of the accumulated value is fed-back into the modulo-N adder for adding modulo N to the accumulated value in the next iteration. N of the modulo-N adder is the same integer as in the modulo-N counter.
    Type: Grant
    Filed: May 28, 2007
    Date of Patent: November 30, 2010
    Assignee: PMC Sierra Inc.
    Inventors: William Dean Warner, Richard Edmund Ryan
  • Patent number: 7836219
    Abstract: An invention is provided for authenticating software associated with an embedded device on a motherboard. An embodiment includes executing an option ROM BIOS for the embedded device. If a bit pattern read from a first memory located on the host card does not match a predetermined bit pattern, the option ROM BIOS is terminated. In another embodiment, a first memory address is provided to the address lines of a memory device located on the host card and a first set of data is output from the memory device, followed by a second memory address to output a second set of data. The second memory address is equal to the first memory address plus the maximum addressable size of the memory device. The first set of data is compared to the second data, and the option ROM BIOS is terminated if the first and second sets of data do not match.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: November 16, 2010
    Assignee: PMC-Sierra US, Inc.
    Inventors: Fadi A. Mahmoud, Ganapathy S. Sridaran