Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: A hybrid balanced code is formed from a low rate (narrow bandwidth) balanced code and a high rate (wide bandwidth) low density code. Data encoded using the hybrid balanced code is transmitted between a first communication network entity and a second communication network entity. The hybrid code enables a system having a hybrid transmitter to transmit either a low rate stream detectable by a low rate receiver or a hybrid stream, from which the low rate data may be detected by a low rate receiver while both the high rate data and the low rate data may be detected by a high rate receiver.

Abstract: Apparatus and methods modulate the slew rate of high-speed edges of a differential digital signal. High-speed digital signals carried over printed circuit boards, backplanes, cables, and the like can radiate electromagnetic waves. These electromagnetic waves can cause electromagnetic interference (EMI), and are tightly regulated by appropriate agencies, such as the FCC. Common mode radiation from differential signals can also cause EMI. By modulating the slew rates of the rising and falling edges of the differential signal, and by applying negative feedback, symbol-rate related spurs can be spread over a wider frequency range than conventional spread spectrum clocking (SSC) techniques, and thus should generally be capable of greater EMI reduction than conventional SSC techniques.

Abstract: A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a global error-counter, coupled to the OLT, for counting FEC-correctable errors, for each ONU, from a data stream from the GPON; and a CPU for extracting an ONU status, indicative of a faulty ONU, contingent on the errors from the global error-counter. A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a grant-start error-counter, coupled to the OLT, for counting grant-start errors, for each ONU, from a data stream from the GPON; a grant-end error-counter, coupled to the OLT, for counting grant-end errors for each ONU; and a CPU for extracting an ONU status, indicative of a faulty ONU, contingent on a parameter selected from the group consisting of the grant-start errors, the grant-end errors, and a combination thereof.

Abstract: A method for dynamic bandwidth allocation (DBA) in a passive optical network (PON) comprises the steps of: in a configuration stage, dividing a predetermined grant cycle into N parts, dividing by an optical line terminal (OLT) a plurality of optical network units (ONUs) into N ONU groups and in each cycle part, concurrently allocating grants to ONUs of one ONU group while having the ONUs of at least one other ONU group send reports and data to the OLT. In a preferred embodiment, the cycle is divided into two fixed half cycles.

Abstract: The present invention discloses methods for reducing power consumption in a PON while maintaining service continuity, the method including the steps of: providing an OLT operationally connected to at least one ONU; triggering a sleep request for at least one requesting ONU; upon receiving a sleep acknowledgement, activating a sleep mode for at least one requesting ONU according to a sleep period designated in the sleep request; and terminating the sleep mode according to the sleep period. Preferably, the sleep acknowledgement is transmitted from the OLT to the requesting ONU. Preferably, the sleep period is executed by a sleep command in the sleep acknowledgement. Preferably, the method further includes the step of: upon completion of the sleep period, transmitting buffered data traffic from the OLT to a sleeping ONU. Preferably, the step of transmitting is performed without the sleeping ONU being re-registered and without causing packet reordering.

Abstract: A system for redundancy in Ethernet passive optical networks (EPONs) facilitates fast recovery from failure (less than 50 msec), path redundancy of the fiber optic network, and location redundancy of the OLTs. An optical networking unit (ONU) in a normal state monitors input communications, and when the input communications are quiet for a predetermined minimum length of time, the ONU transitions to a lenient state in which: the ONU accepts old and new security keys; upon receiving a packet: the ONU updates an ONU timestamp based on the packet's timestamp; and the ONU transitions to the normal state of operation. While the ONU is in the lenient state if a packet is not received for a predetermined given length of time the ONU transitions to a deregistered state. In this system, main and standby OLTs do not require synchronization of security parameters or synchronization for differences in fiber lengths.

Abstract: In a passive optical network, dynamic bandwidth allocation and queue management methods and algorithms, desgiend to avoid fragmentation loss, guarantee that a length of a grant issued by an OLT will match precisely the count for bytes to be transmitted to an ONU.

Abstract: Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

Abstract: A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.

Abstract: An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the effective number of bits (ENOB) required from an ADC of a receiver can vary. The power consumption of certain ADC topologies, such as pipelined converter topologies, can vary with the number of bits. One embodiment dynamically varies the ENOB of an ADC to more optimally consume power. This can extend battery life.

Abstract: An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator is defined to consider a different portion of the multiple requestors when selecting a requestor to be serviced by the master to which the arbitrator is assigned. Each arbitrator is further defined to select a requestor from the different portion of the multiple requestors, such that selection of a particular requestor is not duplicated among the plurality of arbitrators. Additionally, requestor selection by each of the plurality of arbitrators is performed in a same clock cycle.

Abstract: The signal strength of an out-of-channel interferer is estimated by measuring the transition density of the sign of the down-converted signal. RF interferers at a higher or lower frequency than the desired RF signal appear as high frequency content in the down-converted signal, thus increasing the likelihood of zero-crossings.

Abstract: A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined to select a different one of the multiple requestors to be serviced by the master to which the arbitrator is assigned. Also, the plurality of arbitrators is defined to make their requestor selections in the same clock cycle. Additionally, the plurality of arbitrators is defined to make their requestor selections such that selection of a particular requestor is not duplicated among the plurality of arbitrators.

Abstract: Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.

Abstract: The present invention provides a novel structure that can be used to filter certain selected frequencies of common mode signals. The structure comprises a stub connected in parallel to a transmission line with termination at the end. It is suitable for implementation on printed circuit boards or backplanes, but it can be also used within the chip, either on die or package substrate. The structure can be also used as an equalizer, and can be used in designing an analog equalizer for high-speed circuits.

Abstract: A method and apparatus are provided for finding the maxima and minima from a set of inputs data. Given a master set K[0 . . . N?1] of N keys, the current invention can pre-compute a comparison matrix, find the maximum key KMAX or minimum key KMIN from the master set K[0 . . . N?1] and indicate the key position index PMAX of the maximum key or PMIN of the minimum key. Given a subset S[0 . . . M?1] of M keys where the subset S[0 . . . M?1] belongs to the master set K[0 . . . N?1], the current invention can also find the maximum key SMAX or minimum key SMIN from the subset S[0 . . . M?1] and indicate the reference key position index PMAX of the maxima SMAX or PMIN of the minima SMIN in the master set K[0 . . . N?1]. The current invention can also find a specific rank of key (example 5th largest key or 6th smallest key) and return the reference key index position in the master set K[0 . . . N?1].

Abstract: A method and system for preventing loss of data in a computer interface board during power failure includes providing a secondary data path to a non-volatile storage element from a cache memory of the computer interface board. Components in the secondary data path, such as the cache memory and non-volatile storage element, are powered by a secondary power supply. The cache memory of the computer interface board is a volatile memory. The secondary data path with the non-volatile storage element enables reliable memory operation during both normal and power fail modes. A power failure at the computer interface board is detected. The power failure may result in incomplete transactional data within the cache memory. Upon detection of power failure, the incomplete transactional data at the cache memory is transmitted to the non-volatile storage element through the secondary data path using the power from the secondary power supply.

Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Abstract: Delay measurement and delay calibration methods and apparatus are described for use within distributed wireless base stations employing a remote radio head topology. The methods and apparatus are usable in any system that requires accurate delay measurement and/or constant delay through an electronic device. The methods and apparatus for measuring delay embody a highly accurate distributed delay measurement architecture that handles multiple delay paths within distributed wireless base stations employing a remote radio head topology. The method and apparatus are amenable to implementation with current integrated circuit technology. The methods and apparatus for calibrating electronic delay within distributed base stations employing a remote radio head topology are useful for implementing distributed wireless base stations where transmit diversity is desired.