Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Abstract: A fan-out semiconductor package includes a layer of adhesive covering a temporary carrier, a first redistribution layer disposed on the layer of adhesive, the first redistribution layer including a first metal layer having recessed areas. Metal pillars are plated to a first group of the recessed areas in the first metal layer. A semiconductor chip next is bonded to a second group of the recessed areas and a molding compound covers the semiconductor chip. The molding compound is then ground to expose tops of the metal pillars. A second redistribution layer including a second passivation layer adhering to the molding compound and a second metal layer covering openings exposing the tops of the metal pillars are then added.

Abstract: Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure.

Abstract: A semiconductor device package includes an encapsulation layer, a die, at least one trace stiffener, and a redistribution layer. The encapsulation layer has an opening. The die is disposed in the opening of the encapsulation layer. The redistribution layer is formed above the die and the encapsulation layer. The least one trace stiffener are formed on the redistribution layer above boundaries of the encapsulation layer and the die for reinforcing a structure of the redistribution layer above the boundaries of the encapsulation layer and the die.

Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Abstract: A semiconductor device includes a first chip, a spacer, and a second chip. The first chip and the spacer are disposed on a substrate. The second chip has a first half end portion disposed on a first half end portion of the first chip, and a second half end portion disposed on the spacer. The height of the spacer is substantially equal to the height of the first chip.

Abstract: A POP structure includes a first package structure, an interposer, and a second package structure. The first package structure includes a first carrier, a first chip, conductive structures, and a first insulation encapsulation. The first carrier has a first surface and a second surface opposite to the first surface. The first chip and the conductive structures are disposed on the first surface of the first carrier. The first insulation encapsulation is formed on the first surface of the first carrier and encapsulates the conductive structures and the first chip. Top surfaces of the conductive structures are exposed through the first insulation encapsulation and are coplanar. The interposer is disposed on and electrically connected to the first package structure. The second package structure is disposed on and electrically connected to the interposer. A manufacturing method of a POP structure is also provided.

Abstract: A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. The chip is disposed on the inner surface of the substrate. The first encapsulation body is formed on the inner surface of the substrate and encapsulates the chip. The second encapsulation body is formed on the first encapsulation body and a periphery area of the inner surface to encapsulate sidewalls and a top surface of the first encapsulation body and cover the periphery area of the inner surface. Wherein, the Young's modulus of the second encapsulation body is less than the Young's modulus of the first encapsulation body. The heat sink is attached to the second encapsulation body. Thereby, the design of the heat-dissipating semiconductor package utilizes multiple encapsulation bodies to reduce the package warpage after installing the heat sink.

Abstract: A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.

Abstract: A fan-out multi-chip package has a first redistribution layer and a plurality of chips encapsulated in an encapsulant. A dielectric layer and a second redistribution layer are formed on the encapsulant. A bottom surface of the encapsulant is formed when forming the encapsulant. The first redistribution layer has a plurality of connecting surfaces exposed on the bottom surface of the encapsulant. The dielectric layer is formed on the bottom surface of the encapsulant without covering the connecting surfaces. The second redistribution layer includes a plurality of bump pads coupled to the connecting surfaces. The fan-out circuitry is covered by the dielectric layer. Thereby, a multi-chip package is able to reduce possible damages to the active surfaces and bonding pads of the chips during packaging process.

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A redistribution circuit layer is formed on a first carrier. A die is disposed on the redistribution circuit layer. An encapsulant is formed to encapsulate the die. The first carrier is removed to expose a surface of the redistribution circuit layer. A plurality of recesses are formed on the surface of the redistribution circuit layer. A plurality of conductive terminals are formed corresponding to the recesses on the redistribution circuit layer. Another manufacturing method of a package structure is also provided.

Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

Abstract: Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure.

Abstract: A stackable semiconductor package and manufacturing method thereof are provided. The stackable semiconductor package includes carrier, first RDL, encapsulation layer, vertical interposers, second RDL, and chip. The carrier has first surface in which the first RDL and the encapsulation layer are formed thereon. The first RDL includes first pads and second pads. The encapsulation layer covers the first RDL and has outer surface. The vertical interposers are disposed in the encapsulation layer to electrically connect with the first RDL. The second RDL is formed on the outer surface to electrically connect with the vertical interposers. The carrier includes terminal holes and chip-accommodating hole. The terminal holes correspondingly expose the second pads. The chip-accommodating hole exposes the first pads. The chip is mounted on the encapsulation layer through the chip-accommodating hole to electrically connect with the first pads.

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

Abstract: A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. The second chip is disposed on the first chip and exposes the first pads. The pillar bumps are respectively disposed on a plurality of second pads of the second chips. The encapsulant encapsulates the first chip and the second chip and exposes a top surface of each second stud bump. The first conductive vias penetrate the encapsulant and connect the first stud bumps. Each first conductive via covers the rough surface of each first stud bump.

Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

Abstract: A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one active surface among all active surfaces are not covered by the stacked chips. A plurality of flip-chip bumps of a dummy flip chip are coupled to the electrodes of the chips. An encapsulant encapsulates the chip stacked assembly and the flip-chip bumps. The encapsulant has a planar surface. The flip-chip bumps have a plurality of bonding surfaces exposed from and coplanar to the planar surface. A redistribution layer is disposed on the planar surface and includes a plurality of fan out circuits electrically connected the bonding surfaces of the flip-chip bumps. Thus, the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping.

Abstract: A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.