Abstract: A basic storage unit management circuit includes a receiving circuit, a transmitting circuit, a first buffer, and an idle basic storage unit controller. The first buffer is arranged to store a bit map, wherein the bit map includes a plurality of first bits that correspond to a plurality of basic storage units, respectively, and each of the plurality of first bits is arranged to label whether a corresponding basic storage unit is an idle basic storage unit. The idle basic storage unit controller is coupled to the receiving circuit, the transmitting circuit, and the first buffer, and is arranged to manage the bit map stored by the first buffer, and process at least one basic storage unit of at least one packet that is received by the receiving circuit or is transmitted by the transmitting circuit.

Abstract: A method for image compression and a circuit system thereof are provided. In the method, pixel values of an image are obtained. A compression scenario is decided, for example, a uniform-quantization manner or a non-uniform-quantization manner is used for an M-bit image being compressed to an N-bit image so as to decide codeword sections for the image. Every codeword section has a codeword distance. The codeword sections have a fixed codeword distance in the uniform-quantization manner. Alternatively, in the non-uniform-quantization manner, the image can be divided into multiple codeword sections having different codeword distances according to a brightness distribution. Afterwards, a random number is generated for deciding codeword and index for original value of each of the pixels. An index table is accordingly formed. The index table is provided for obtaining the codeword in a decoding process by querying a codebook with the index.

Abstract: An asymmetric image transmission method and an electronic device thereof are provided. The asymmetric image transmission method is applicable to transmission of an image signal from a transmitter to a receiver and includes: modifying, by the transmitter, a first image pixel length in the image signal that conforms to a four-byte mode to a second image pixel length of a three-byte mode; transmitting a plurality of image pixels of the second image pixel length in the three-byte mode respectively through three transmission lanes of a transmission interface; and modifying, by the receiver, the second image pixel length of the image pixels to the first image pixel length of the four-byte mode to obtain the image signal.

Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.

Abstract: A control integrated circuit (IC) for maintaining video output to a conditional access module (CAM) with aid of reference clock regeneration, an associated television receiver and an associated method are provided. The control IC may include an input control circuit, a frame processing circuit, a clock control circuit, and an output control circuit. The input control circuit receives a transport stream (TS) data signal from a demodulator circuit, the frame processing circuit performs frame processing operations on the TS data signal to prepare a plurality of frames, the clock control circuit generates a second reference clock signal according to the TS valid signal to be a replacement for a first reference clock signal, and the output control circuit outputs the plurality of frames to the CAM according to the second reference clock signal, to allow the CAM to perform conditional access (CA) control for the television receiver.

Abstract: A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

Abstract: An impedance control circuit includes a configuration channel interface, three resistors and two transistors. The configuration channel interface is coupled to a universal serial bus device. The first resistor has a first terminal coupled to the configuration channel interface. The first transistor has a first terminal coupled to a second terminal of the first resistor, and a second terminal coupled to a system voltage terminal. The second transistor has a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the system voltage terminal. The second resistor has a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a control terminal of the second transistor. The third resistor has a first terminal coupled to the second terminal of the second resistor, and a second terminal coupled to the system voltage terminal.

Abstract: A processing circuit, a network device, and a processing method for anomaly detection are provided. The network device includes a processing circuit and network ports. The processing circuit includes a physical layer (PHY) transmission unit, a PHY control unit, a state detection unit, and a reset unit. The processing circuit performs steps of: switching from operating in the first operation state to operating in a second operation state by the PHY control unit according to an operation request; obtaining a current operation state of the PHY control unit by the state detection unit; determining whether the current operation state and the second operation state are identical by the state detection unit; and driving the reset unit to reset the PHY control unit to an initial state if the current operation state and the second operation state are not identical.

Abstract: A wireless transceiver device and matching circuits thereof are provided. In the wireless transceiver device, a first matching circuit is electrically coupled to an antenna and a transmission circuit. In the first matching circuit, a first capacitor is electrically coupled to the antenna and a first switching component, the first switching component is electrically coupled to a reference voltage, a first active component having a first threshold voltage is coupled in parallel with the first switching component, a first inductor of an inductor pair is electrically coupled to the antenna and the reference voltage, and a second inductor of the inductor pair is electrically coupled to the transmission circuit. When the voltage across the first active component is greater than the first threshold voltage, the first active component is turned on, thus reducing the voltage across the first switching component to protect the first switching component.

Abstract: A display control method includes: receiving a first video signal provided by a first video source device to display one or more first images in the first video signal on a display device; when the display device is displaying the one or more first images, establishing a connection with a second video source device and receiving a second video signal provided by the second video source device through the connection; generating one or more composite images based on the one or more first images in the first video signal and one or more second images in the second video signal without receiving a user control input; and displaying the one or more composite images on the display device.

Abstract: A multi-link device includes a first link queue, a second link queue, a control circuit, a first transmitter and a second transmitter. The control circuit includes a common queue for buffering a plurality of packets, each packet having a sequence number. The control circuit obtains a minimum sequence number of all packets in the first link queue and the second link queue, computes a maximum sequence number according to the minimum sequence number and a block acknowledgment window size, determines whether to allocate a set of packets from the common queue according to the maximum sequence number, and if so, allocates the set of packets to the first link queue and/or the second link queue. The first transmitter transmits a packet from the first link queue to a first receiving device, and the second transmitter transmits a packet from the second link queue to a second receiving device.

Abstract: A processing method and circuit of key derivation based on hash message authentication codes (HMAC) are provided. The processing circuit includes a memory and an HMAC processor. The HMAC processor performs the following steps: loading a plaintext file and an initial vector into an HMAC procedure during an initial operation round so as to generate a temporary vector and a common vector, generating a first combined block data according to the plaintext file and the temporary vector during at least one other operation round, loading the first combined block data and the common vector into the HMAC procedure so as to generate a new temporary vector, recursively performing the HMAC procedure on the new temporary vector and the common vector until all of the at least one other operation round is completed, and outputting the new temporary vector as a target key.

Abstract: An audio processing device includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: A leakage current blocking circuit and a leakage current blocking method for a decoupling capacitor are provided. A first end of the decoupling capacitor is coupled to a power voltage. The leakage current blocking circuit is coupled between a second end of the decoupling capacitor and a ground voltage, and the leakage current blocking circuit includes at least one switch. The at least one switch is used to provide a channel for the decoupling capacitor to be coupled to the ground voltage when the decoupling capacitor is not damaged, and when the decoupling capacitor is damaged, the at least one switch is turned off to block a leakage current of the decoupling capacitor.

Abstract: A method for compressing video signals based on adaptive compression rate and a circuit system thereof are provided. In the method, a digital signal processor is used to process a video so as to frame-by-frame obtain statistical data, for example, a maximum of compressed data. The maximum of compressed data of a previous frame is used to determine a compression state of a current frame. The compression state of the frame allows the processor to decide a direction to adjust a compression ratio. Next, statistical data of the previous frame is used to decide a stride to adjust the compression ratio. The statistical data can be a maximum of compressed data and a quantization table scale referred to rendering a prediction curve that allows the processor to determine the stride. A compression ratio is then determined according to the direction and the stride of adjustment.

Abstract: A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.

Abstract: A code checking method includes: causing a compiler to generate a map file and a low-level code file(s) according to a high-level code file(s); obtaining target function information from the map file; finding a target code file from the low-level code file(s); obtaining a first return command of a target function name of the target function information from the target code file; traversing the low-level code file(s) to obtain each calling module name and a second return command of each calling function name; obtaining a second storage area of each calling module name from the map file; and generating a check failure result when calling of a target function name by each calling function name is not complied with a bank-switching compile form according to a first storage area of the target function information, the first return command, each second storage area, and each second return command.

Abstract: An amplifying circuit, comprising: a charging circuit, comprising a plurality of first transistors electrically coupled to a target device; and an output circuit, comprising a plurality of second transistors electrically coupled to the target device. After at least one of the first transistors turns on and the second transistors turn off such that the charging circuit charges the target device to a predetermined voltage, at least one of the first transistors and at least one of the second transistors simultaneously turn on for a predetermined time, and then at least one of the second transistors turns on but the first transistors turns off.

Abstract: A communication device for handling a Peak-to-Average Power Ratio (PAPR), includes a transforming module, configured to perform a first plurality of inverse fast Fourier transforms (IFFTs) on a plurality of coefficients in a scene according to a first inverse fast Fourier transform (IFFT) size and the scene, to obtain a plurality of results; a processing module, coupled to the transforming module, configured to obtain a plurality of norms of the plurality of results, and to obtain a plurality of values of the plurality of coefficients; and a transmitting module, coupled to the processing module, configured to perform a second plurality of IFFTs on a plurality of frequency-domain signals according to a second IFFT size, the plurality of coefficients with the plurality of values and the scene, to obtain a plurality of time-domain signals, wherein the second IFFT size is greater than the first IFFT size.

Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.