Abstract: A feed forward echo cancellation device includes a first impedance circuit, a second impedance circuit, and an echo cancellation current generator circuit. The first impedance circuit is configured to output a first current to a node in response to a transmission current. The second impedance circuit is configured to output a second current to a node in response to the transmission current. The echo cancellation current generator circuit is configured to drain an echo cancellation current from the node. The node is connected to an input terminal of a programmable gain amplifier circuit via a gain control circuit, and the gain control circuit is configured to set a gain of the programmable gain amplifier circuit.

Abstract: A switch and a scheduling method for packet forwarding of the same are provided. The switch includes a plurality of absorb queues, a plurality of egress ports, and an absorb scheduler. Each of the egress ports includes a plurality of egress queues that are respectively connected to one of the absorb queues that are different from one another. The scheduling method includes: generating a priority state for each of the egress queues of each of the egress ports; a packet forwarding priority state of each of the absorb queues is determined according to the priority state of each of the egress queues connected thereto; and the absorb scheduler selecting one of the absorb queues to send a packet stored therein to a target egress queue of a target egress port to be sent to, according to the priority state of each of the egress queues.

Abstract: A multi-link device includes a first link queue, a second link queue, a control circuit, a first transmitter and a second transmitter. The control circuit includes a common queue for buffering a plurality of packets, each packet having a sequence number. The control circuit obtains a minimum sequence number of all packets in the first link queue and the second link queue, computes a maximum sequence number according to the minimum sequence number and a block acknowledgment window size, determines whether to allocate a set of packets from the common queue according to the maximum sequence number, and if so, allocates the set of packets to the first link queue and/or the second link queue. The first transmitter transmits a packet from the first link queue to a first receiving device, and the second transmitter transmits a packet from the second link queue to a second receiving device.

Abstract: The present invention provides a receiver including a decoder, an upscale circuit and a color space conversion circuit. The decoder is configured to decode a video stream to generate a base layer and an enhancement layer. The upscale circuit is configured to perform an upscaling operation on the base layer to generate an upscaled base layer, wherein the upscaled base layer comprises luminance values of a plurality of pixels of a frame, and the enhancement layer comprises residuals of the plurality of pixels of the frame. The color space conversion circuit is configured to use a conversion matrix to combine the upscaled base layer and the enhancement layer to generate output video data.

Abstract: A firmware upgrade method and a firmware upgrade system based on a multi-stream transmission mode of a DisplayPort interface are provided. The firmware upgrade method includes: configuring a host to obtain firmware information of the displays through a DisplayPort auxiliary channel, and select a target display for firmware upgrade; and executing a firmware upgrade process including: configure the host to send a upgrade start command and firmware upgrade data to the target display; and configuring each display to: determine whether the upgrade start command and the firmware upgrade data reach the target display, and if not, send the upgrade start command and the firmware upgrade data to the next display, if so, execute a firmware upgrade preparation process according to the upgrade start command, and write the firmware upgrade data into the firmware storage device of the target display.

Abstract: The present invention discloses an analog-to-digital conversion circuit having remained time measuring mechanism is provided. A digital-to-analog conversion (DAC) circuit samples input voltages to generate output voltages. A comparator compares the output voltages to generate a comparison result. A control circuit switches a configuration of the DAC circuit by using a digital code according to the comparison result. A comparison determining circuit sets a stage indication signal at a finished state after the comparison result is generated. A comparison stage counting circuit accumulates a termination number according to the stage indication signal to set a conversion indication signal at the finished state when the termination number reaches a predetermined number. A time accumulating circuit starts to accumulate a remained time when the conversion indication signal is at the finished state and finishes accumulation when a sampling indication signal is at a sampling state.

Abstract: An adaptive image shading correction method and an adaptive image shading system are provided. The method includes: configuring an image capturing device to obtain a current frame; and configuring a processing unit to: divide the current frame into blocks; select block pairs from the blocks, in which each of the block pairs includes an inner block and an outer block; perform a filtering process for each of the block pairs to determine whether a brightness condition, a saturation condition, a hue similarity condition, and a sharpness similarity condition are met; in response to obtaining filtered block pairs, calculate a sum similarity threshold based on hue statistical data, a saturation difference, and a brightness difference; and use filtered blocks with individual thresholds less than the sum similarity threshold to calculate a shadow compensation value to adjust the current frame.

Abstract: A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Abstract: A testing system includes a signal generator circuit, a jitter modulation circuit, and an oscilloscope circuit. The signal generator circuit is configured to generate a clock pattern signal with a single clock pattern frequency. The jitter modulation circuit is configured to generate a jitter signal. A device-under-test is configured to receive an input signal. The input signal is a combination signal of the clock pattern signal and the jitter signal. The device-under-test includes a clock data recovery circuit and is further configured to generate an output signal according to the input signal. The oscilloscope circuit is configured to receive the output signal for determining performance of the clock data recovery circuit.

Abstract: A dual-band transform circuit structure includes a first transmission line, a second transmission line, and a conductive layer. The first transmission line has a first input terminal, a first output terminal, and a second output terminal. The second transmission line has a second input terminal, a third input terminal, a third output terminal, and a fourth output terminal. The second input terminal is coupled to the first output terminal, and the third input terminal is coupled to the second output terminal. The conductive layer is stacked with the first transmission and the second transmission line. The conductive layer includes a first hollow pattern. The first hollow pattern and the second transmission line are overlapped in a top view.

Abstract: An asymmetric spiral inductor is provided. The asymmetric spiral inductor includes a first winding, a second winding and a third winding. The first winding has a first end and a second end and is implemented in the ultra-thick metal (UTM) layer of a semiconductor structure. The second winding, which has a third end and a fourth end, is implemented in the re-distribution layer of the semiconductor structure and has a first maximum trace width. The third winding, which has a fifth end and a sixth end, is implemented in the UTM layer of the semiconductor structure and has a second maximum trace width smaller than the first maximum trace width. The second and third ends are connected through a first through structure, the fourth and fifth ends are connected through a second through structure, and the first and sixth ends are the two ends of the asymmetric spiral inductor.

Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

Abstract: A power source equipment is configured to provide a power to a powered device in a power over Ethernet. The power source equipment includes a first port, a second port, and a control circuit. The first port is configured to perform a power classification on the powered device, and provide a first voltage to the powered device in a first stage. The second port is configured to provide a second voltage to the powered device in a second stage. The control circuit is configured to disable the second port in the first stage, and configured to control the second port to output the second voltage and increase the first voltage in the second stage.

Abstract: An integrated circuit includes a first coil and a second coil. The first coil is disposed on the first side of the integrated circuit. The second coil is disposed on the second side of the integrated circuit, and is partially overlapped with the first coil at a junction. The first coil is not interlaced with the second coil at the junction.

Abstract: An IC, comprising: a package; a target circuit; and a heating circuit, configured to receive a heating signal to heat at least testing portion of the target circuit to a first predetermined temperature based on the heating signal. The target circuit and the heating circuit are within the package. An IC testing method using such IC is also disclosed.

Abstract: An electronic device debug method, applied to a target electronic device with an error detecting device, a debug device, and a transceiving device, comprising: (a) detecting an error of the target electronic device by the error detecting device to generate error information corresponding to the error; (b) transmitting the error information to the transceiving device through the debug device; (c) transmitting the error information to a remote electronic device through the transceiving device by a wireless network; and (d) controlling the target electronic device to perform a debug procedure corresponding to the error information by the remote electronic device, through the transceiving device.

Abstract: An Ethernet power sourcing equipment (PSE) and a power management method thereof are provided. The Ethernet PSE includes a plurality of ports and a controller. Each port is coupled to a powered device (PD), to supply power to the PD through the port when the PD is in a power supply stage. When the PD enters a startup stage before the power supply stage, the controller calculates a remaining power quota based on a power quota allocated to the PD.

Abstract: A Bluetooth internet protocol packet transmitting device and method are provided. The device includes a Bluetooth protocol stack, a Bluetooth controller and a host control interface. The Bluetooth protocol stack is configured to store an internet protocol stack and a host control interface driver. The Bluetooth controller generates at least one data packet based on an internet protocol packet, wherein the at least one data packet corresponds to an asynchronous connection data format. The Bluetooth controller transmits the at least one data packet to the host control interface driver. The host control interface driver determines whether the at least one data packet is an asynchronous connection data packet. When the host control interface driver determines that the at least one data packet is the asynchronous connection data packet, the at least one data packet is transmitted to the internet protocol stack.

Abstract: A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

Abstract: The present application provides an optical network method and associated apparatus. The method includes: receiving uplink burst time assignment information; and enabling or disabling a laser module of a local end according to the uplink burst time assignment information.