Abstract: An isolated selector and an associated electronic device are provided. The isolated selector receives first data and second data from a first functional circuit and a second functional circuit, respectively, and the isolated selector includes an isolated component, wherein the isolated component receives the first data and generates isolated data according to a control signal and the first data. In addition, the isolated selector selects one of the first data and the second data to be output as output data of the isolated selector. When the isolated selector selects the second data to be output as the output data according to the control signal, the isolated component set the isolated data to be a fixed value according to the control signal, in order to prevent operations of the first functional circuit from interfering with the output data of the isolated selector.

Abstract: A digital pre-distortion circuit and a method for reducing clipping noise in a digital pre-distortion circuit are provided. The digital pre-distortion circuit includes a pre-distorter, a clipping logic, an error extraction circuit, a filter and a compensation circuit. The pre-distorter performs a pre-distortion operation according to an input signal to generate an initial pre-distortion signal, and the clipping logic clips the initial pre-distortion signal to generate a clipped pre-distortion signal. In addition, the error extraction circuit calculates a difference between the initial pre-distortion signal and the clipped pre-distortion signal to generate a clipped error signal, and the filter performs filtering on the clipped error signal to generate a filtered error signal, wherein the compensation circuit compensates the clipped pre-distortion signal according to the filtered error signal to generate an output signal.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device is arranged to operably transmit a first device information corresponding to the first member device and a second device information corresponding to the second member device to the Bluetooth host device. The Bluetooth host device is arranged to operably receive the first device information and the second device information transmitted from the first member device. The Bluetooth host device is further arranged to operably establish a Bluetooth connection with the first member device and conduct pairing procedure with the first member device after receiving a selection command.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit.

Abstract: The application discloses a circuit, including: a positive-terminal p-type transistor; a negative-terminal p-type transistor; a positive-terminal n-type transistor, wherein the positive-terminal p-type transistor and the positive-terminal n-type transistor are cascoded between a first reference voltage and a second reference voltage; a negative-terminal n-type transistor, wherein the negative-terminal p-type transistor and the negative-terminal n-type transistor are cascoded between the first reference voltage and the second reference voltage; a first positive-terminal capacitor, a top plate of the first positive-terminal capacitor is coupled to a gate of the positive-terminal n-type transistor; a first negative-terminal capacitor, a top plate of the first negative-terminal capacitor is coupled to a gate of the negative-terminal n-type transistor; a first control circuit, arranged to generate a first control signal to bottom plates of the first positive-terminal capacitor and the first negative-terminal capac

Abstract: An audio system is proposed, dynamically playing optimized audio signals based on user position. A sensor circuits dynamically senses a target space to generate field context information. First speaker and second speaker are arranged for audio playback. A host device recognizes a user from the field context information, determines the user position corresponding to the target space, and adaptively assigns the user position as a target listening spot. A sensor circuit contains a camera capturing an ambient image out of the target space. A control circuit utilizes a user interface circuit to perform a configuration procedure which determines location, size and acoustic attribute information of an ambient object, and the control circuit accordingly performs a channel-based compensation operation on the target listening spot to generate optimized first channel audio signal and second channel audio signal.

Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device is arranged to operably transmit an auto-pair request, a first device information corresponding to the first member device, and a second device information corresponding to the second member device to the Bluetooth host device. The Bluetooth host device is arranged to operably receive the auto-pair request, the first device information, and the second device information transmitted from the first member device. The Bluetooth host device is further arranged to operably establish a Bluetooth connection with the first member device and conduct pairing procedure with the first member device according to the auto-pair request.

Abstract: The present invention provides an encoder including a quantization circuit, a control circuit and an encoding circuit is disclosed. The quantization circuit is configured to generate quantized data corresponding to a CTU according to image data, wherein the CTU comprises at least one TU. The control circuit is configured to determine a number of allocated bits for each TU in the CTU, where the number of allocated bits for each TU is determined based on a sum of remaining bits of the TUs that have been encoded. The encoding circuit is configured to encode each TU to obtain encoded data according to the number of allocated bits of the TU in the CTU.

Abstract: A lead frame adapted to be applied to a quad flat no-lead (QFN) package structure is provided. The QFN package structure includes a die. Bumps are disposed on an active surface of the die. The lead frame includes a central region and a peripheral region surrounding the central region. The lead frame includes a plurality of leads. The leads are at the peripheral region. A solder pad is disposed on an upper surface of one of two ends of each of the leads. The solder pad of each of the leads is configured to be directly soldered to a corresponding one of the bumps on the active surface of the die. For each of the leads, the end having the solder pad is nearer to the central region of the lead frame with respect to the other end. A manufacturing method of semiconductor device is also provided.

Abstract: A digital pre-distortion circuit includes a memoryless non-linear operating circuit, an intermodulation shaping filter circuit, and a signal combination circuit. The memoryless non-linear operating circuit performs a memoryless non-linear operation upon a transmission signal to generate a first signal, wherein the first signal is an output simulation signal of a radio frequency (RF) power amplifier under the memoryless effect, and the first signal includes a signal component corresponding to the transmission signal and a signal component corresponding to an intermodulation signal of the transmission signal. The intermodulation shaping filter circuit filters the first signal to generate a second signal, wherein the second signal simulates an intermodulation signal generated by the RF power amplifier in response to the transmission signal under a memory effect. The signal combination circuit combines the transmission signal and the second signal to generate a pre-distortion signal.

Abstract: A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of character images respectively corresponds to a plurality of characters of a character encoding format. The computing circuit is coupled with the first memory, and is configured to receive first update data generated by encoding input data according to the character encoding format, and is configured to use the first update data to update text data in a second memory. When the computing circuit reads the text data in the second memory, the computing circuit is configured to: search among the plurality of character images to find a plurality of target images corresponding to the text data; and output first display data according to the plurality of target images, in which the first display data is for generating a first display picture including the plurality of target images.

Abstract: A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit.

Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes a first sub-trace and a second sub-trace. The first sub-trace and the second sub-trace form a plurality of first wires together at a first side of the inductor device, and form a plurality of second wires together at a second side of the inductor device. The second sub-trace is coupled to one terminal of the first sub-trace at a first node. The third sub-trace and the fourth sub-trace form a plurality of third wires together at the first side of the inductor device, and form a plurality of fourth wires together at the second side of the inductor device. The fourth sub-trace is coupled to one terminal of the third sub-trace at a second node. The capacitor is coupled to the first node and the second node.

Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes a first and a second sub-trace. The first sub-trace includes first wires, and the second sub-trace includes second wires. The second sub-trace is coupled to the first sub-trace at a first node. The first and the second wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The second trace includes a third and a fourth sub-trace. The third sub-trace includes third wires, and the fourth sub-trace includes fourth wires. The fourth sub-trace is coupled to the third sub-trace at a second node. The third and the fourth wires are disposed to each other in an interlaced manner, and located at an outer side of the inductor device. The capacitor is coupled between the first and the second node.

Abstract: An inductor structure includes a first connecting component, a second connecting component, and a center-tap terminal. In the inductor structure, a first port of the first connecting component is coupled to a first wire, and a second port of the first connecting component is coupled to a second wire. The second connecting component disposed above or beneath the first connecting component in an interlaced manner. The center-tap terminal is coupled to one of the first connecting component and the second connecting component. The center-tap terminal is disposed on a layer that is different from the layer where the first connecting component is disposed or the layer where the second connecting component is disposed.

Abstract: A first access point in a mesh network includes a transceiver and a processor. The processor is coupled to the transceiver, and is used to determine whether a second access point transmitting a beacon belongs to the mesh network upon detecting the beacon. If so, the processor is used to determine whether the beacon includes first channel switch announcement information, and if so, configure the transceiver to transmit second channel switch announcement information, and configure the first access point to switch to a target channel. The first channel switch announcement information and the second channel switch announcement information include information of the target channel.

Abstract: An aggregation packet forwarding method and a system for the same are provided. The method includes: configuring a first NIC to transmit to-be-forwarded packets to an aggregation module; configuring the aggregation module to generate an aggregated packet according to packet characteristics of the to-be-forwarded packets; configuring a first processing unit to execute a first NIC driver to process the aggregated packet generated by the aggregation module and send them to an L2 forwarding module; configuring the L2 forwarding module to transmit the aggregated packet according to an L2 forwarding table; configuring a second processing unit to execute a second NIC driver to process the aggregated packet and send the aggregated packet to a deaggregation module; configuring the deaggregation module to deaggregate the aggregated packet into the to-be-forwarded packets, and send the to-be-forwarded packets to the second NIC; and configuring the second NIC to receive the to-be-forwarded packets.

Abstract: The present invention provides a multi-die package including main die, a memory die, a first set of pins and a second set of pins. The main die includes a memory controller, a first set of pads, a second set of pads and a third set of pads. The memory die is coupled to the first set of pads and the second set of pads of the main die. The first set of pins is coupled to the third set of pads of the main die. The second set of pins is coupled to the second set of pads of the main die. The memory controller accesses the memory die through the first set of pads and the second set of pads, and the memory controller accesses a memory chip external to the multi-die package through the second set of pads and the third set of pads.