Patents Assigned to Realtek Semiconductor
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Patent number: 10915688Abstract: Disclosed is an IC layout design method capable of improving a result of an integrated circuit (IC) layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to an initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining an updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.Type: GrantFiled: February 26, 2020Date of Patent: February 9, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Shu-Yu Chang, Shih-Jung Hsu, Han-Chieh Hsieh, Yu-Cheng Lo, Cheng-Yu Tsai
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Patent number: 10915732Abstract: Disclosed is an image processing method capable of processing facial data and non-facial data differentially. The method is carried out by an image processing device, and includes the following steps: determining a facial region, a non-facial region and a transitional region according to a face detection result of an image, in which the transitional region is between the facial region and the non-facial region; and executing different processes for the data of the facial region, the data of the non-facial region and the data of the transitional region respectively.Type: GrantFiled: May 7, 2019Date of Patent: February 9, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Kai Liu, Zhong-Yi Qiu, Wen-Tsung Huang
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Patent number: 10917130Abstract: The present disclosure provides a signal receiving apparatus having anti-RFI mechanism that includes an ADC circuit, an equalization circuit and a clock recovery circuit. The ADC circuit performs conversion of an input analog signal according to an internal clock signal, to generate an input digital signal. The equalization circuit equalizes the input digital signal such that the clock recovery circuit adjusts a phase of the internal clock signal and extracts a frequency by performing statistics on phase deviation amount information in a unit of a time window. The clock recovery circuit discards a corresponding phase deviation amount when a signal interference parameter of one of a sub time window is larger than a threshold value to update the phase deviation amount information, and generates an adjusting signal to adjust a frequency of the internal clock signal accordingly.Type: GrantFiled: June 29, 2020Date of Patent: February 9, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yu-Xuan Huang, Liang-Wei Huang
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Patent number: 10911642Abstract: The present invention discloses an image processing circuit including an image processing unit, a frame rate adjusting circuit and a phase detection and control circuit. In operations of the image processing circuit, the image processing unit is configured to process an input image signal including a plurality of frames to generate a processed image signal including a plurality of processed frames, the frame rate adjusting circuit is configured to adjust a row number of vertical blanking intervals of at least one of the processed frames according to a control signal, to generate an output image signal including at least one adjusted frame, and the phase detection and control circuit is configured to determine a phase relationship of the input image signal or the processed image signal and the output image signal to generate the control signal.Type: GrantFiled: April 21, 2020Date of Patent: February 2, 2021Assignee: Realtek Semiconductor Corp.Inventors: Huan-Wen Chen, Po-Hsien Wu
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Patent number: 10909290Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.Type: GrantFiled: March 3, 2020Date of Patent: February 2, 2021Assignee: Realtek Semiconductor Corp.Inventors: I-Hsiu Lo, Yung-Jen Chen, Yu-Lan Lo, Shu-Yi Kao
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Patent number: 10911079Abstract: A transmitter operating in a communication system is provided. The transmitter includes an encoding circuit and a modulation circuit. The transmitter is configured to generate multiple encoded bits according to an encoding relationship, in which the encoding relationship is corresponding to a code rate and a minimum distance, and the minimum distance is greater than a reciprocal of the code rate. The modulation circuit is configured to generate a transmission signal according to the encoded bits, such that the encoded bits are transmitted over multiple subcarriers, and each encoded bit is transmitted via a subcarrier. The encoding relationship is corresponding to multiple output codewords, and the minimum distance represents a minimum Hamming distance between two distinct output codewords. One of the output codewords includes the encoded bits.Type: GrantFiled: February 19, 2020Date of Patent: February 2, 2021Assignee: Realtek Semiconductor Corp.Inventors: John Timothy Coffey, Der-Zheng Liu, Hsuan-Yen Chung
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Patent number: 10909669Abstract: A contrast adjustment system includes a memory and a processor. The memory stores instructions. The processor is configured to access and execute the instructions to: access an image with a plurality of pixels, wherein the pixels are corresponding to a plurality of intensity values; generate a histogram based on a distribution of the intensity values in a range from an intensity lower bound to an intensity upper bound; divide the histogram into four sub-histograms based on a median value of the intensity values; enlarge the four sub-histograms based on a predetermined parameter; remap the four sub-histograms to form a gamma curve based on a cumulative distribution function; and apply the gamma curve to pixels of another image.Type: GrantFiled: January 3, 2020Date of Patent: February 2, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chung-Yan Chih, Kai Liu, Wen-Tsung Huang
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Patent number: 10911819Abstract: Disclosed is a multimedia pipeline device including first pipeline circuits and a processor. The first pipeline circuits include: a first circuit generating first data according to input data and recording characteristic information of the input data; and a second circuit generating second data according to the first data and recording characteristic information of the first data. The processor determines whether the characteristic information of the input data and the characteristic information of the first data are correct according to first and second prestored information respectively, in which at least a part of the first prestored information is recorded by the first circuit according to verified input data in advance and at least a part of the second prestored information is recorded by the second circuit according to verified first data in advance, and the verified input data and the input data originate from the same multimedia test file.Type: GrantFiled: April 12, 2019Date of Patent: February 2, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Ching-Lung Chen
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Patent number: 10902807Abstract: A display device for motion blur reduction effect is provided which includes a liquid-crystal display panel, a driving module, a backlight module and a processing module. The processing module receives input display data to generate output display data. The output display data includes an output frame data section for performing data transmission with an output pixel clock higher than an input pixel clock and an output blank section within the same frame time. The processing module drives the liquid-crystal display panel to generate a display frame according to the output display data and controls the backlight module to turn on within the output blank section after the liquid-crystal display panel finished reacting to output frame data corresponding to the output frame data section.Type: GrantFiled: July 23, 2019Date of Patent: January 26, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Li-Ang Chen, Ting-Lun Hsu
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Patent number: 10902896Abstract: The present disclosure is related to a memory circuit. The memory includes a memory controller and a memory interface coupled between the memory controller and a memory device. The memory controller is configured to generate an output signal that is transmitted to the memory device. The memory interface includes a feedback path configured to receive the output signal and generates a feedback signal in response to the output signal and a variable reference voltage. The memory controller further includes a data register so as to sample the feedback signal in response to a clock signal having a phase with an adjustable shift.Type: GrantFiled: August 22, 2018Date of Patent: January 26, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ching-Sheng Cheng, Wen-Wei Lin
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Publication number: 20210013845Abstract: A circuit includes a digital-to-analog conversion circuit, an amplifying circuit, a mixing circuit, and an analog-to-digital converter. The digital-to-analog conversion circuit is configured to receive and convert audio data in the digital domain and output audio data in the analog domain. The audio data includes a main-tone component. The amplifying circuit is configured to output an audio signal according to the audio data in the analog domain. The mixing circuit is configured to eliminate the main-tone component according to the audio data in the analog domain and the audio signal and to output a feedback signal. The analog-to-digital converter is configured to convert the feedback signal from the analog domain to the digital domain.Type: ApplicationFiled: July 7, 2020Publication date: January 14, 2021Applicant: REALTEK SEMICONDUCTOR CORP.Inventor: Chih-Kang Chien
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Patent number: 10892717Abstract: A circuit includes a first common-source amplifier configured to receive a first voltage at a first gate node and output a first current to a first drain node in accordance with a first source voltage at a first source node; a second common-source amplifier configured to receive a second voltage at a second gate node and output a second current to a second drain node in accordance with a second source voltage at a second source node; a first diode-connected device configured to couple the first source node to a DC (direct current) node; a second diode-connected device configured to couple the second source node to the DC node; and a source-degenerating resistor inserted between the first source node and the second source node.Type: GrantFiled: March 5, 2019Date of Patent: January 12, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Publication number: 20210004520Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.Type: ApplicationFiled: December 5, 2019Publication date: January 7, 2021Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
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Patent number: 10887929Abstract: The present disclosure provides a resource allocation method. The resource allocation method includes the following steps: selecting multiple first selected virtual nodes according to multiple virtual pheromonal trails on multiple virtual edges, in which the first selected virtual nodes forms at least one virtual tour, and the virtual tour includes multiple first virtual edges; updating the virtual pheromonal trails on the virtual edges according to virtual distances corresponding to the first virtual edges of the virtual tour; selecting multiple second selected virtual nodes according to the updated virtual pheromonal trails on the virtual edges, in which the second selected virtual nodes form at least one resulting virtual tour; allocating the resource blocks to selected user pairs according to the resulting virtual tour.Type: GrantFiled: August 2, 2019Date of Patent: January 5, 2021Assignee: Realtek Semiconductor Corp.Inventors: Ting-Wei Lai, Hsuan-Jung Su, Der-Zheng Liu
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Patent number: 10887058Abstract: A signal detector includes oversampling circuitries and a detector circuitry. The oversampling circuitries are configured to receive a first signal and a second signal from a channel, and to sequentially sample the first signal and the second signal according to a plurality of clock signals to generate a plurality of signal difference values, and to compare the plurality of signal difference values with a reference difference value, in order to generate a plurality of detection signals. The detector circuitry is configured to generate a noise indication signal according to the plurality of detection signals, in order to indicate whether the first signal and the second signal are noises.Type: GrantFiled: June 4, 2019Date of Patent: January 5, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ming-Hui Tung, Wei-Chi Chen
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Patent number: 10886901Abstract: A circuit includes multiple stages cascaded in a ring topology such that each stage has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage. Each stage includes a MOS transistor of a first type, a MOS transistor of a second type and a resistor. The MOS transistor of a first type receives a first input that is output from the preceding stage, and outputs a second output to the alternate-preceding stage. The MOS transistor of a second type receives a second input that is output from the alternate-succeeding stage, and outputs a first output to the succeeding stage. The resistor provides coupling and level-shifting between the first output and the second output.Type: GrantFiled: February 14, 2020Date of Patent: January 5, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Patent number: 10887533Abstract: An infrared crosstalk compensation method includes capturing an original image of a scene, where the original image includes a plurality of original pixels, the original pixels are arranged in a two-dimensional array according to a first axial direction and a second axial direction, and each original pixel has a red subpixel value, a green subpixel value, a blue subpixel value, and an infrared subpixel value. The method further includes: obtaining compensated values of the red, green, blue, and infrared subpixel values according to the original image, a compensation axial direction, a plurality of red, green, blue compensation coefficients corresponding to the compensation axial direction, and compensation equations; and obtaining a compensated image according to the compensated values of the red, green, blue, and infrared subpixel values.Type: GrantFiled: April 10, 2019Date of Patent: January 5, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Zhong-Yi Qiu, Wen-Tsung Huang
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Patent number: 10887711Abstract: Disclosed is a sound recording circuit capable of adjusting microphone sensitivity and preventing sound cracks caused by overly loud sound. The sound recording circuit includes: a microphone bias circuit configured to provide a bias voltage for a microphone circuit; an AC coupling capacitor configured to output an analog input signal according to a microphone signal of the microphone circuit; an analog amplifier circuit configured to output an analog output signal according to the analog input signal; an analog-to-digital converter configured to output a digital input signal according to the analog output signal; a digital amplifier circuit configured to output a digital output signal according to the digital input signal; and a signal detector configured to control an analog gain of the analog amplifier circuit, a digital gain of the digital amplifier circuit, and the bias voltage of the microphone bias circuit.Type: GrantFiled: August 27, 2019Date of Patent: January 5, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Tsung-Peng Chuang
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Patent number: 10879924Abstract: The present invention provides a delta-sigma modulator and associated signal processing method, wherein the signal processing method includes: generating a first difference signal according to a difference between an input signal and a first feedback signal; filtering the first difference signal to generate a filtered signal; generating a second difference signal according to a difference between the filtered signal and a second feedback signal; quantizing the second difference signal to generate an output signal; using a first DAC to generate the first feedback signal according to the output signal; using a second DAC to generate a first analog signal according to the output signal; delaying the output signal to generate a first delayed output signal; using a third DAC to generate a second analog signal according to the first delayed output signal; and generating the second feedback signal according to the first analog signal and the second analog signal.Type: GrantFiled: July 30, 2019Date of Patent: December 29, 2020Assignee: Realtek Semiconductor Corp.Inventor: Xiaobo Zhou
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Patent number: 10879899Abstract: An apparatus includes: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the first inverter connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the second inverter connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively; a first resistor connected to a first DC (direct-current) voltage to the first source node; and a second resistor connected to a second DC voltage to the second source node.Type: GrantFiled: August 15, 2017Date of Patent: December 29, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin