Abstract: A wireless communication device that includes an antenna module, a first communication circuit and a second communication circuit is provided. The first communication circuit performs communication by using a first communication protocol and transmits a test signal via the antenna module. The second communication circuit performs communication by using a second communication protocol and receives the test signal to calculate an isolation index based on an actual received power thereof. The second communication circuit determines that the antenna module includes two antennas when the isolation index is smaller than a threshold value to operate the first and the second communication circuits under a dual-antenna operation mode. The second communication circuit determines that the antenna module includes one antenna when the isolation index is not smaller than the threshold value to operate the first and the second communication circuits under a shared-antenna operation mode.

Abstract: The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.

Abstract: A user pairing method is provided. The method includes the following steps: selecting a first uplink user device among the uplink set; selecting a first downlink user device among the downlink set; determining whether the first uplink channel gain corresponding to the first uplink user device is greater than a second uplink channel gain corresponding to the first downlink user device, to generate a first determination result; determining whether a first signal to noise plus interference ratio (SINR) perceived at the first downlink user device is greater than a first SINR threshold, to generate a second determination result; forming the first uplink user device and the first downlink user device as a first user pair in a full duplexing (FD) mode when the first determination result and the second first determination result are positive.

Abstract: A skin color image gamut weight detecting method and a device thereof are provided. The method includes: receiving an image including first color components and second color components; obtaining a skin color region, a skin color category, and a first gamut; obtaining first color component values and first cardinal numbers according to the first color components; obtaining second color component values and a plurality of second cardinal numbers according to the second color components; obtaining a second gamut and a weight center according to the skin color category, the first cardinal numbers, the second cardinal numbers, the first color component values, and the second color component values; obtaining a first weight area and a second weight area according to the first gamut and the second gamut; and obtaining a skin color gamut weight map according to the weight center, the first weight area, and the second weight area.

Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.

Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.

Abstract: A wireless transceiver device includes an antenna unit for receiving a first RF signal or transmitting a second RF signal. A first matching unit is connected to the antenna unit and a receiving circuit. The first matching unit and the receiving circuit form a first signal receiving channel for receiving the first RF signal when the first RF signal is a high/low gain RF signal. A second matching unit is connected to the antenna unit and a transmitting circuit. The second matching unit and the transmitting circuit form a signal transmitting channel for transmitting the second RF signal. A bypass coupling circuit is connected to the receiving circuit and the second matching unit. The second matching unit, the bypass coupling circuit, and the receiving circuit form a second signal receiving channel for receiving the first RF signal when the first RF signal is a middle gain RF signal.

Abstract: A helical stacked integrated inductor formed by a first inducing unit and a second inducing unit includes a first helical coil and a second helical coil. The first helical coil is substantially located at a first plane and includes a first outer turn and a first inner turn. The first inner turn is surrounded by the first outer turn. The first helical coil forms a part of the first inducing unit and a part of the second inducing unit. The second helical coil is substantially located at a second plane different from the first plane and overlaps the first helical coil. The second helical coil forms a part of the first inducing unit and a part of the second inducing unit. The first helical coil and the second helical coil are stacked in a staggered arrangement.

Abstract: An inductor structure includes a first curve metal component, a second curve metal component, and a connection component. The first curve metal component is disposed on a layer. The layer is located at a first plane, the first curve metal component is located at a second plane, and the first plane is perpendicular to the second plane. The second curve metal component is disposed on the layer. The second curve metal component is located at the second plane. The connection component is coupled to the first curve metal component and the second curve metal component.

Abstract: The present invention discloses a Wireless Local Area Network (WLAN) and Bluetooth (BT) device including a WLAN circuit and a BT circuit. The WLAN circuit starts a WLAN slot according to a beacon of a beacon signal from an access point and executes WLAN communication. The WLAN slot ends after a measured reception time point of the beacon so as to prevent missing the beacon. The BT circuit starts a BT slot after the end of the WLAN slot and executes BT communication. If the BT slot is shorter than the period of the beacon signal minus the WLAN slot, the WLAN circuit earns additional time to start an extended WLAN slot after the end of the BT slot for carrying on the WLAN communication. The extended WLAN slot is not longer than the period of the beacon signal minus the sum of the WLAN and BT slots.

Abstract: Disclosed is a method feasible for a hidden non-ASCII SSID. The method is carried out by a to-be-set wireless device and includes: broadcasting a beacon signal carrying predetermined data detectable to an already-set wireless device; wirelessly connecting to the already-set wireless device; receiving the profile data of a target wireless device from the already-set wireless device and then wirelessly disconnecting the already-set wireless device, wherein the SSID of the target wireless device is a hidden non-ASCII SSID; acquiring packets for establishment of connection between the already-set wireless device and the target wireless device according to the profile data; obtaining the raw data of the SSID according to the content of the packets and then connecting to the target wireless device according to the profile data and the raw data; and transmitting a connection success message to the already-set wireless device via the target wireless device.

Abstract: Disclosed is a transmission gate circuit including a control voltage generating circuit, a high voltage transmission circuit and a low voltage transmission circuit. The high and low voltage transmission circuits are coupled between an input terminal and an output terminal. The control voltage generating circuit generates two voltage groups according to an input voltage of the input terminal and an enable voltage and thereby controls the high and low voltage transmission circuits with the two voltage groups respectively. When the enable voltage is high, one voltage group includes identical voltages while a difference between any of the identical voltages and any voltage of the other voltage group is not higher than a predetermined voltage; when the enable voltage is low, each voltage group includes decremental voltages. The high/low voltage transmission circuit is turned on when the enable voltage is high and the input voltage is high/low.

Abstract: A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

Abstract: A successive approximation analog-to-digital converter (SAR ADC) and an operation method thereof are provided. The SAR ADC, which alternately operates in a sampling phase and a comparison and switching phase, includes a switch-capacitor digital-to-analog converter (DAC), a comparator, a successive approximation register and a control circuit. The switch-capacitor DAC including multiple capacitors. The control circuit is configured to (A) control a top plate of a first capacitor and a top plate of a second capacitor to be coupled to an analog input signal during the sampling phase; (B) control the first capacitor and the second capacitor to be active and inactive, respectively, in the comparison and switching phase according to a reference code after the sampling phase finishes; and (C) switch a terminal voltage of at least one of the capacitors during the comparison and switching phase according to the comparison results of the comparator.

Abstract: The invention discloses a calibration circuit and a calibration method for an analog-to-digital converter (ADC). The calibration method of the ADC includes the following steps: (a) resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (b) changing a terminal voltage of at least one capacitor in the first capacitor group; (c) the ADC generating a first digital code; (d) after the first digital code is obtained, resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (e) changing a terminal voltage of at least one capacitor in the third capacitor group; and (f) the ADC generating a second digital code. The first digital code and the second digital code are used to correct the output of the ADC.

Abstract: A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).

Abstract: The present invention discloses a counting circuit of a performance monitor unit, capable of preventing a cycle counter from being suspended due to the occurrence of an overflow. An embodiment of the counting circuit includes a cycle counter and an event counter. The cycle counter starts counting from a beginning number according to a cycle of a clock signal during enablement duration, and when a count of the cycle counter reaches a count maximum of the cycle counter during the enablement duration, the cycle counter changes a level of a trigger signal and then counts from the beginning number again. The event counter counts according to change of the level of the trigger signal. Accordingly, the counting circuit is operable to obtain a total cycle number of the clock signal in the enablement duration according to the count of the cycle counter and a count of the event counter.

Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Abstract: A transmitter circuit includes a slew rate control circuit, a hysteresis circuit, a logic control circuit, and an amplifier circuit. The slew rate control circuit controls a slew rate of an input signal to generate a first output signal. The hysteresis circuit generates a first control signal according to the first output signal. The logic control circuit generates a second control signal and a third control signal according to the input signal and the first control signal. The amplifier circuit generates a second output signal according to the first output signal, the second output signal, the second control signal, and the third control signal.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.