Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.

Abstract: A computer system, operated on a system platform, includes memories and a controller circuit. The memories include a first memory and a second memory, in which the first memory include s a first storage space and a second storage space, and a size of a total storage space of the second memory is the same as a size of the first storage space. The memories are coupled in parallel with the controller circuit, and the controller circuit assigns at least one first data zone to the first storage space and the second memory based on a kernel of the system platform, and assigns a second data zone to the second storage space. A data access frequency of the second data zone is lower than a data access frequency of the at least one first data zone.

Abstract: A 3D electromagnetic bandgap circuit includes: a dielectric layer having a first surface and an opposing second surface; a spiral element positioned on the first surface; a first surrounding element positioned on the first surface and surrounding the spiral element, but does not touch with the spiral element; a plane element positioned on the second surface and including a notch; a second surrounding element positioned on the second surface and surrounding the plane element, but does not touch with the plane element, wherein the second surrounding element further includes a protruding portion extending toward the notch; a first via passing through the dielectric layer, the spiral element, and the protruding portion; a second via passing through the dielectric layer, the plane element, and the first surrounding element; and a third via passing through the dielectric layer, the plane element, and the first surrounding element.

Abstract: The present invention provides an interface circuit, wherein the interface circuit includes a switching circuit, an over-voltage detection circuit and a control signal generating circuit. In the operations of the interface circuit, the switching circuit is configured to receive an input signal from an input terminal, and selectively transmit the input signal to an internal circuit. The over-voltage detection circuit is configured to detect whether a voltage level of the input signal is greater than a threshold value, and accordingly generate at least one over-voltage signal. The control signal generating circuit is configured to generate a control signal according to said at least one over-voltage signal, to control the switching circuit to be in one of three or more states.

Abstract: A signal processing circuit includes: a printed circuit board (PCB) including a first surface layer, a second surface layer, a first reference layer, and a second reference layer, wherein the first and second surface layers are positioned on opposing side of the PCB while the first reference layer and the second reference layer are positioned between the first and second surface layers; a memory chip positioned on the first surface layer; a controller chip positioned on the second surface layer; a first set of signal lines arranged on the first surface layer and coupled with the memory chip, wherein all signal lines in the first set of signal lines does not cross each other; and a second set of signal lines arranged on the second surface layer and coupled with the controller chip, wherein all signal lines in the second set of signal lines does not cross each other.

Abstract: A color-shift calibration method is provided to process an image including pixels, in which an arrangement of the pixels corresponds to a Bayer color filter array and the pixels include first green pixels, second green pixels, red pixels and blue pixels. The color-shift calibration method includes the steps outlined below. A regional gradient change of the first and the second green pixels within a neighboring region corresponding to a target green pixel is calculated. An intensity difference between the first and the second green pixels is calculated. When the regional gradient change is smaller than a gradient threshold and the intensity difference exceeds an intensity threshold range, a pixel calibration is performed on the target green pixel based on the first and the second green pixels.

Abstract: A crystal oscillator includes an inverter configured to receive a first voltage at a first node and output a second voltage at a second node, a stacked-diode feedback network inserted between the first node and the second node, a waveform shaper configured to couple the second node to a third node in accordance with the first voltage, a crystal inserted between a fourth node and a fifth node, wherein the fourth node is coupled to the third node, and the fifth node is coupled to the first node, a first shunt capacitor inserted between the fourth node and a ground node, and a second shunt capacitor inserted between the fifth node to and the ground node.

Abstract: A network communication device includes a transceiver circuit and a controller. The transceiver circuit is configured to transmit or receive data via a plurality of antennas. The controller is coupled to the transceiver circuit, and the controller is configured to control the transceiver circuit to establish a transmission channel to provide a connection to a first electronic device. If a number of antennas of the first electronic device is less than a number of the plurality of antennas, the controller is configured to reconfigure the transmission channel as multiple channels, in order to provide the connection to the first electronic device via a first channel of the multiple channels, and the first channel corresponds to at least one first antenna of the plurality of antennas.

Abstract: Disclosed are an image tuning device and an image tuning method. The image tuning method includes the following steps: dividing an image area into a plurality of blocks for executing brightness adjustment individually, in which the blocks include a target block and at least one neighboring block; receiving pixel data of the target block to calculate a target block brightness value; receiving pixel data of the at least one neighboring block to calculate at least one neighboring block brightness value; calculating a calculated brightness value of a target pixel within the target block according to the target block brightness value and the at least one neighboring block brightness value; and generating an adjusted brightness value of the target pixel by adjusting an original brightness value of the target pixel according to the calculated brightness value.

Abstract: A dual-mode signal amplifying circuit includes: a first and a second input terminals for receiving differential input signals; two output terminals for providing differential output signals; a first through a third current sources; a first switch positioned between the first current source and a first node, and controlled by the first input terminal; a second switch positioned between the first current source and a second node, and controlled by the second input terminal; a third switch positioned between the first node and a fixed-voltage terminal, and controlled by a third node; a fourth switch positioned between the second node and a fixed-voltage terminal and controlled by the third node; a fifth switch positioned between the second current source and a fixed-voltage terminal, and controlled by the first node; and a sixth switch positioned between the third current source and a fixed-voltage terminal, and controlled by the second node.

Abstract: A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range.

Abstract: A phase-locked loop circuit includes a delay phase-locked loop and a sub-sampling phase-locked loop. The delay phase-locked loop phase locks a first reference clock and a second reference clock to an input clock, and includes a phase correction circuit, an integrator, a first sub-sampling phase detector, and a first charge pump. The sub-sampling phase-locked loop is configured to generate an output clock with a predetermined phase-locked loop frequency, and the output clock is phase-locked to the first reference clock, the sub-sampling phase-locked loop includes a second sub-sampling phase detector, a second charge pump, a phase frequency detecting circuit, a voltage controlled oscillator and a first frequency divider. The first sub-sampling phase detector and the second sub-sampling phase detector have a symmetric circuit structure, and a first charge pump circuit and a second charge pump circuit have a symmetric circuit structure.

Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.

Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Abstract: A helical stacked integrated transformer formed by a first inductor and a second inductor includes a first helical coil that has a first outer coil and a first inner coil, a second helical coil that shares an overlapped region with the first helical coil and has a second outer coil and a second inner coil, and a connection structure that connects the first helical coil and the second helical coil. The first inner coil is located inside the first outer coil and the second inner coil is located inside the second outer coil. The first inductor includes a part of the first helical coil and a part of the second helical coil. The second inductor includes a part of the first helical coil and a part of the second helical coil.

Abstract: A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

Abstract: An audio codec circuit includes: an audio processing circuit; an output driver circuit for generating an analog output signal based on the output of the audio processing circuit; an analog signal pin for outputting the analog output signal to an active amplifier; a multifunction signal pin for providing different signal transmission functionalities according to the configuration of the audio processing circuit; at least one de-pop switch arranged between the analog signal pin and a first fixed-voltage terminal or between the multifunction signal pin and a second fixed-voltage terminal; and a de-pop switch control circuit, coupled with the audio processing circuit and the at least one de-pop switch, arranged to operably control the at least one de-pop switch based on the instruction from the audio processing circuit.

Abstract: A multi-member Bluetooth network includes: a main Bluetooth circuit capable of directly communicating with a remote Bluetooth device through a Bluetooth transmission approach; and an auxiliary Bluetooth circuit capable of indirectly communicating with the remote Bluetooth device through the main Bluetooth circuit. When the auxiliary Bluetooth circuit becomes more closer to the remote Bluetooth device than the main Bluetooth circuit, the main Bluetooth circuit instructs the auxiliary Bluetooth circuit to utilize the device identification data and multiple Bluetooth connection parameters of the main Bluetooth circuit to directly communicate with the remote Bluetooth device through a Bluetooth transmission approach by imitating the main Bluetooth circuit, and the main Bluetooth circuit then indirectly communicates with the remote Bluetooth device through the auxiliary Bluetooth circuit.

Abstract: An electronic component of an electronic device, a method of starting an electronic device, and an encryption method. The electronic device includes a key storage unit that stores a first key, a key protection circuit that controls access of the key storage unit, and a storage unit that stores a second key and encrypted booting instructions. The method of starting an electronic device includes steps of: reading the first key from the key storage unit; reading the second key from the storage unit; generating a third key according to the first key and the second key; using the third key to decrypt the encrypted booting instructions; and executing the booting instructions.

Abstract: An inductor device includes at least two wires and at least two switches. Each of the at least two wires includes an opening, and the openings are disposed correspondingly to each other. One of the at least two switches is coupled to two terminals of the opening of one of the at least two wires. Another one of the at least two switches is coupled to one terminal of the opening of the one of the at least two wires and one terminal of the opening of another one of the at least two wires in an interlaced manner. If the one of the at least two switches is turned on, one of the at least two wires forms an inductor; if another one of the at least two switches is turned on, both of the at least two wires form the inductor.