Abstract: A sampling clock testing circuit includes a clock circuit, a processing circuit and a phase determining circuit. The clock circuit generates a clock signal and switches phases of the clock signal according to a horizontal synchronous signal. The processing circuit samples a data signal according to the clock signal with the phases to generate pixel data groups each of which is corresponding to one phase. The phase determining circuit generates calculated values according to the pixel data groups, in which each phase is corresponding to one calculated value. The phase determining circuit selects a specific calculated value from the calculated values according to a predetermined condition, and determines a specific phase corresponding to the specific calculated value. The processing circuit samples a subsequent data signal according to the clock signal switched to the specific phase to generate subsequent pixel data.

Abstract: The present invention provides a clock generating circuit, wherein the clock generating circuit includes a phase detector, an integral path, a proportional path, a bias path and an oscillator. In the operations of the clock generating circuit, the phase detector generates a detection result according to a reference signal and a feedback signal, a first charge pump within the integral path generates a first control signal according to the detection result, a second charge pump within proportional path generates a second control signal according to the detection result, a low-pass filter within the bias path filters the first control signal to generate a third control signal, and the oscillator generates a clock signal according to the first control signal, the second control signal and the third control signal.

Abstract: A signal processing circuit includes a signal receiving circuit for generating a first input signal and a second input signal; a signal output circuit for generating a first output signal and a second output signal according to the first input signal and the second input signal; a negative impedance circuit, for amplifying the first input signal at the first input terminal to generate a first amplified input signal at the second output terminal, and for amplifying the second input signal at the second input terminal to generate a second amplified input signal at the first output terminal; a first capacitor; a second capacitor; wherein the first capacitor and the second capacitor have different DC voltage levels at both terminals, such that the impedance-signal variation rate of the negative impedance circuit is lower than a predetermined level.

Abstract: An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.

Abstract: Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

Abstract: The present invention provides a calibration method applied to a DAC, wherein the calibration method includes the steps of: generating a first digital input signal to the DAC to generate a first analog signal; using an ADC to generate a first digital output signal according to the first analog signal; generating a second digital input signal to the DAC to generate a second analog signal; swapping a polarity of the second analog signal to generate a swapped signal; using the ADC to generate a second digital output signal according to the swapped signal; and generating a digital calibration signal according to the first digital output signal and the second digital output signal, to control a calibration circuit to generate an analog calibration signal or to determine a polarity direction of a DC offset that is to be calibrated.

Abstract: The present invention discloses a defective pixel compensation method and device capable of compensating for defective pixels of an RGBIr sensor. An embodiment of the method includes: determining the type of a sensor; determining a plurality of sample positions according to the type of the sensor and the position of a target pixel; obtaining the values of a plurality of reference pixels in a sampling window according to the sample positions; determining a value range and at least one compensation value(s) according to the values of the reference pixels; determining whether an input value of the target pixel is within the value range; when the input value is within the value range, outputting the input value as an output value of the target pixel; and when the input value is outside the value range, outputting one of the compensation value(s) as the output value of the target pixel.

Abstract: A buck-boost switching regulating method includes outputting a mode signal according to an input voltage and an output voltage, generating one of a plurality of triangle waves according to the mode signal, comparing a feedback signal and a reference signal to generate an error signal, comparing the error signal and the generated triangle wave to output a comparison signal, and generating a set of switch signals according to the comparison signal. The feedback signal is related to the output voltage. The waveform of the triangle wave generated when the mode signal represents a buck-boost mode is larger than that when the mode signal represents a adjusting mode.

Abstract: This invention discloses an image processing method and an image processing device for filtering images. The image processing method includes the following steps: (A) generating a weight for each reference pixel, the image including multiple reference pixels and the magnitude of the weight being associated with a similarity between the reference pixel to which the weight corresponds and a target pixel; and (B) performing an infinite impulse response (IIR) filtering operation according to the weights, a pixel value of the target pixel, and the pixel values of the reference pixels to obtain an IIR-filtered value of the target pixel.

Abstract: A method comprises: using a plurality of gain stages cascaded in a ring topology to form a ring oscillator configured to output an oscillation signal; controlling a supply voltage of said ring oscillator using a low-speed DAC (digital-to-analog converter) in accordance with a coarse control word; providing a capacitive load at an inter-stage node of said ring oscillator using a varactor array controlled by a control voltage array; establishing said control voltage array using a high-speed DAC array in accordance with a fine control word; adjusting the coarse control word upon a start-up to make an oscillation frequency of said oscillation signal approximately equal to target value; and adjusting the fine control word in a closed loop manner in accordance with a detection of a timing error of said oscillation signal.

Abstract: This invention discloses a network data prediction method, a network data processing device, and a network data processing method. The network data processing method is applied to a device that implements an open systems interconnection model (OSI model) and includes the following steps: generating a first data block and a second data block according to the OSI model; processing the first data block based on an error detection method to generate a first check code; encoding the first data block and the first check code to generate a first network data; transmitting the first network data; and receiving a second network data that includes a second check code; generating a target data according to a portion of the second data block and a portion of the second network data; and checking the target data according to the second check code.

Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, successive approximation register (SAR) circuitries, and noise shaping circuitries. The capacitor arrays sample an input signal by turns, in order to provide a sampled input signal. The SAR circuitries perform an analog-to-digital conversion by turns according to a combination of the sampled input signal, a first residue signal, and a second residue signal, in order to generate digital outputs. The noise shaping circuitries receive a corresponding residue signal of the first residue signal the second residue signal in response to the analog-to-digital conversion, and to shape and transmit the corresponding residue signal to the SAR circuitries.

Abstract: An electronic system includes a feedforward equalizer, a feedback equalizer, an RFI canceler, and a control circuit. The feedforward equalizer and the feedback equalizer are configured to adjust the channel response of a transmission channel in the electronic system. The RFI canceler is configured to cancel the RFI presence in the electronic system. When the RFI canceler is off, the controller is configured to turn on the RFI canceler according to a signal error value before RFI cancelation, an error term of the electronic system, or an SNR of the electronic system.

Abstract: An audio playback device having a noise-cancelling mechanism is provided that includes an external sound-receiving circuit that receives external noise, a fixed-coefficient filtering circuit, an operation circuit, an audio playback circuit, an internal sound-receiving circuit and an adjusting circuit. The fixed-coefficient filtering circuit generates an inverted signal including a main and an auxiliary inverted components having the same amplitude and phases orthogonal to each other according to the external noise. The operation circuit multiplies the inverted signal by adjusting parameters to generate an adjusted inverted signal. The audio playback circuit receives and playbacks an audio signal and the adjusted inverted signal to generate a playback result. The internal sound-receiving circuit receives the playback result to generate a received sound signal.

Abstract: The present invention provides a DP to HDMI converter, wherein the DP to HDMI converter comprises a receiving circuit, a signal converter and a transmitter. In the operations of the DP to HDMI converter, the receiving circuit is configured to receive a plurality of input signals, wherein the input signals comprise a plurality of DP signals configured to generate an image frame with variable frame rate. The signal converter is configured to receive the plurality of input signals to generate a plurality of HDMI signals, wherein the signal converter includes a synchronization signal generator for generating a vertical synchronization signal and a horizontal synchronization signal of the plurality of HDMI signals according to a portion of the input signals. The transmitter is configured to output the plurality of HDMI signals.

Abstract: Disclosed is an inverter capable of withstanding a high voltage. The inverter includes a control voltage generating circuit, a high voltage transmission circuit, and a low voltage transmission circuit. The control voltage generating circuit generates a first group of control voltages and a second group of control voltages according to an input voltage, in which one group includes decrement voltages and the other group includes identical voltages. The high/low voltage transmission circuit is coupled between a high/low voltage terminal and an output terminal, wherein when the input voltage is low/high, the high/low voltage transmission circuit is turned on according to the first/second group of control voltages so that an output voltage of the output terminal is equal to a high/low voltage of the high/low voltage terminal.

Abstract: A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.

Abstract: A checking method for checking whether a signal in a chip is interference-free, and the checking method includes the following operations: analyzing, by a processor, a netlist file to acquire a first node for outputting the signal in the chip, in which the netlist file is configured to describe a circuit architecture of the chip; searching, by the processor, candidate nodes associated with the signal according to the netlist file and the first node; and determining, by the processor, whether a first candidate node of the candidate nodes is connected to an anti-interference circuit, in order to check whether the signal is interference-free.

Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes the following steps: controlling the DAC not to receive the output of the quantizer; controlling the SDM to stop receiving signals; inputting a test signal to the DAC; converting the output of the loop filter to a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the result of comparing the digital signal and the preset value.