Abstract: This invention discloses a floating-point number operation circuit and a method thereof. The floating-point number operation circuit is configured to perform a fused multiplication and accumulation (fused mac) operation or a multiplication and accumulation (mac) operation on a first operand, a second operand, and a third operand, or perform a multiplication operation on the first operand and the second operand. The floating-point number operation circuit includes two rounding circuits, a multiplication circuit, a selection circuit, a control circuit, and an addition circuit. The control circuit controls the scheduling of various operations and the use of resources on each calculation path.

Abstract: A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.

Abstract: A dual-mode signal amplifying circuit includes: a first and a second input terminals for receiving differential input signals; two output terminals for providing differential output signals; a first through a third current sources; a first switch positioned between the first current source and a first node, and controlled by the first input terminal; a second switch positioned between the first current source and a second node, and controlled by the second input terminal; a third switch positioned between the first node and a fixed-voltage terminal, and controlled by a third node; a fourth switch positioned between the second node and a fixed-voltage terminal, and controlled by the third node; a fifth switch positioned between the second current source and a fixed-voltage terminal, and controlled by the first node; and a sixth switch positioned between the third current source and a fixed-voltage terminal, and controlled by the second node.

Abstract: Disclosed are a white balance calibration method based on skin color data and an image processing apparatus using the same. By using the method and the image processing apparatus, weight allocation of the skin color data in an input image may be adaptively performed to avoid white balance calibration errors due to excessive skin color data. Therefore, the present disclosure can further solve an issue that in video applications, the white balance calibration is easily interfered by a large amount of the skin color data. Moreover, the present disclosure may be adapted to different color temperatures and may output images having colors closer to actual colors.

Abstract: A background blurred method includes steps as follows: obtaining a color image, an IR light frame image and an IR dark frame image, and calculating a differential image between the IR light frame image and the IR dark frame image to generate a binary image; obtaining a foreground image of the binary image; calculating an IR brightness mean value of the foreground image of the differential image; and filtering the color image to generate a background blurred image according to the IR brightness mean value.

Abstract: Fixed length code (FLC)-based image compression method and device are provided. The FLC-based image compression method for compressing a block containing multiple pixels includes the following steps: determining a first representative pixel and a second representative pixel from the pixels according to the pixel values of the pixels; generating, by interpolation, multiple interpolated pixels according to the first representative pixel and the second representative pixel; generating an index value for each of the pixels according to the first representative pixel, the second representative pixel, and the interpolated pixels; adjusting the first representative pixel and the second representative pixel to generate a first adjusted representative pixel and a second adjusted representative pixel; and using the index values and complete or quantized pixel values of the first adjusted representative pixel and the second adjusted representative pixel to represent the block.

Abstract: Disclosed is a voltage-controlled oscillator (VCO) capable of providing an effective high VCO gain against slow change of an input voltage caused by the variation of manufacturing processes, temperature, voltage, etc. and providing an effective low VCO gain against rapid change of the input voltage for reducing jitter. The VCO includes: an input circuit generating an input current according to an input voltage; a first current supply circuit generating a first output current according to the input current; a second current supply circuit generating a second output current according to the input current; a filter coupled to the input circuit and the second current supply circuit and configured to slow down the influence caused by the variation of the input current on the second current supply circuit; and an oscillating circuit generating an output clock according to the first output current and the second output current.

Abstract: A regulator device includes a first switch, a second switch, a protecting circuit, and a driving circuit. The first switch is configured to receive power supply voltage. One terminal of the second switch and the first switch are coupled at a node. The other terminal of the second switch is coupled to ground. The protecting circuit is coupled to the node, and outputs at least one protecting signal according to the turn on/off state of the first switch and the second switch and the voltage of the node. The driving circuit is coupled to the first switch, the second switch, and the protecting circuit, and turns off the first switch or the second switch according the at least one protecting signal.

Abstract: An Ethernet connection method and an Ethernet device thereof are provided. The Ethernet connection method and the Ethernet device can transmit data with Error Correction Code (ECC) even with only one twisted pair or two twisted pairs when the Ethernet wire cannot transmit with the full four twisted pairs.

Abstract: A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

Abstract: A switch circuit includes: a switching device control circuit receiving a first voltage and a second voltage, a first Type-I switching device coupled to the switching device control circuit and a first control voltage, a first Type-II switch element coupled to the switch control circuit and the first Type-I switch element, and a second Type-II switch element coupled to the first Type-I switch element and the first Type-II switch element. When the second voltage is higher than the first voltage, the switch control circuit turns on the first Type-II switch element in order to turn off the second Type-II switch element; and when the second voltage is higher than the first voltage, the first Type-I switch element is off.

Abstract: The present invention discloses a false color removal method comprising: receiving a current pixel including a first color value, a second color value and a third color value, in which the three color values are composed of a maximum value, a medium value and a minimum value; performing permutation to the maximum value, the medium value and the minimum value to obtain six permutation results; calculating six weighting values, in which a kth weighting value is calculated according to at least a kth permutation result of the six permutation results and the three color values, and the k stands for an integer-variable between one and six; calculating six products, in which a kth product is obtained by multiplying the kth weighting value by the kth permutation result; and using the sum of the six products to update the first, second and third color values.

Abstract: The disclosure is related to a method and a system for detecting a video scan type. In the method, a first frame and a second frame are firstly extracted from a video. The scan lines of each frame can be divided into a top field and a bottom field. A first zipper index of the combination of the top field of the first frame and the bottom field of the second frame is obtained. Further, a second zipper index of the combination of the bottom field of the first frame and the top field of the second frame is also obtained. A zipper index difference between the first zipper index and the second zipper index is calculated and is provided to determine the video scan type as an interlaced-scan video or a progressive-scan video.

Abstract: An integrated inductor includes a first coil, a second coil, a third coil and a fourth coil. The first coil is disposed on a first layer of an integrated circuit structure. The second coil is disposed on the first layer and adjacent to the first coil, in which the first coil and the second coil have same number of turns. The third coil is disposed on a second layer of the integrated circuit structure and above the first coil. The fourth coil is disposed on the second layer and above the second coil, in which the third coil and the fourth coil have same number of turns. The first coil is coupled to and interlaced with the fourth coil disposed on the second layer. The second coil is coupled to and interlaced with the third coil disposed on the second layer.

Abstract: A bandwidth detection device comprises a receiving circuit, for receiving a first plurality of frequency-domain signals on a first subchannel; a filter circuit, coupled to the receiving circuit, for transferring the first plurality of frequency-domain signals to a first plurality of filtered frequency-domain signals according to a filter function; and a processing circuit, coupled to the filter circuit, for comparing the first plurality of frequency-domain signals with the first plurality of filtered frequency-domain signals, to determine whether the first subchannel comprises first transmitted data.

Abstract: A heat dissipation device control method for dissipating heat from an electronic element without self-heat-dissipation function in an electronic device. The method comprises: detecting a first temperature of the electronic element; and controlling the fan of the peripheral element located around the electronic element when the first temperature exceeds the first upper temperature threshold to dissipate the heat from the electronic element.

Abstract: An inductor device includes a first and a second inductor unit. The first inductor unit includes a first and a second wire. The first wire is winded to form circles. The second wire is winded with the first wire to form circles. The first and/or the second wire are winded in an interlaced manner at a first terminal, a second terminal, a first side, and a second side. The second inductor unit includes a third and a fourth wire. The third wire is winded to form circles. The fourth wire is winded with the third wire to form circles. The third and/or the fourth wire are winded in an interlaced manner at a third terminal, a fourth terminal, a third side, and a fourth side. The first wired is coupled to the fourth wired, and the second wired is coupled to the third wired.

Abstract: An image processing method and an electronic apparatus for foreground image extraction include steps: (A) acquiring frame images of a dynamic image, wherein each frame image has an RGB image and an IR image; (B) acquiring an RGB image representing a dark state as an RGB capture image, acquiring an IR image representing a light state as an IR light frame image, and acquiring one IR image representing the dark state as an IR dark frame image; (C) calculating a difference image between the IR light frame image and the IR dark frame image and binarizing the difference image to generate a binarized image; and (D) acquiring a plurality of foreground pixels corresponding to an IR foreground part of the binarized image of the RGB capture image and taking the foreground pixels as the foreground image, thereby reducing the impact of ambient light, background noise and calculation.

Abstract: A device includes a baseband circuit that generates a first digital signal, a digital-to-analog converter (DAC) that converts the first digital signal into a baseband signal, a first mixer that generates a first mixed signal based on the baseband signal and a first reference signal, a second mixer that generates a second mixed signal based on the baseband signal and a second reference signal, a third mixer that generates a down-converted signal based on the first mixed signal and the second mixed signal, and an analog-to-digital converter (ADC) that converts the down-converted signal into a second digital signal. The frequency of the first reference signal is different from the frequency of the second reference signal.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.