Abstract: A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.

Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

Abstract: Disclosed is a voice control system and method thereof. The voice control system is used in an electronic device and works in a sleep mode and a working mode. The voice control system comprises an audio detection module, an audio codec and a control module. Under the sleep mode, the audio detection module continually detects whether there is a wake-up speech in a received first audio data. If yes, the audio detection module generates a first indication signal and temporarily stores the following first audio data. When the control module is woken up by the first indication signal, the voice control system enters the working mode. Under the working mode, the control module drives the audio codec to read and process the temporarily stored first audio data to recognize control speech in the first audio data and to accordingly control the electronic device.

Abstract: A transmitter circuit is provided in the present disclosure. The transmitter circuit includes a first capacitance, a first current pump circuit for charging or discharging the first capacitance to output a first voltage, a second capacitance, and a second current pump circuit for charging or discharging the second capacitance to output a second voltage. A charging rate at which the first current pump circuit charges the first capacitance or a discharging rate at which the first current pump circuit discharges the first capacitance determines a rising slew rate or a falling slew rate of the first voltage. A charging rate at which the second current pump circuit charges the second capacitance or a discharging rate at which the second current pump circuit discharges the second capacitance determines a rising slew rate or a falling slew rate of the second voltage.

Abstract: An oscillator includes a voltage-controlled oscillator (VCO) circuit and a processing circuit. The VCO circuit generates an oscillating frequency according to a digital signal, in which the oscillating frequency is a first oscillating frequency if the digital signal has a first signal value. The processing circuit determines a second signal value of the digital signal according to the first oscillating frequency and a target oscillating frequency, in order to tune the oscillating frequency to a second oscillating frequency. The processing circuit performs an interpolation operation according to a first frequency difference value between the target oscillating frequency and the first oscillating frequency and a second frequency difference value between the second oscillating frequency and the first oscillating frequency to determine a target signal value of the digital signal, in order to adjust the oscillating frequency to the target oscillating frequency.

Abstract: A receiver circuit of a transceiver is disclosed including: a calibration circuit arranged to operably perform an I/Q mismatch calibration operation according to an in-phase detection signal and a quadrature detection signal to generate one or more compensation parameters; a parameter storage circuit; an interference detection circuit arranged to operably generate an estimated signal-to-interference ratio according to the in-phase detection signal and the quadrature detection signal; a receiver control circuit arranged to operably determine whether to discard the one or more compensation parameters, wherein the receiver control circuit stores the one or more compensation parameters into the parameter storage circuit only if the estimated signal-to-interference ratio exceeds a predetermined threshold.

Abstract: A signal processing device includes an acoustic echo cancellation (AEC) circuit, a blocking matrix circuit, a controller, a subtractor, and a filter. The AEC circuit performs an AEC operation based on a far-end signal and a first input signal to generate a processed signal. The blocking matrix circuit suppresses a target signal component of the first input signal and a second input signal, to generate a reference signal. The controller generates a control coefficient based on the processed signal and the second input signal. The subtractor generates an output signal based on the filtered signal and the processed signal. The filter generates the filtered signal in response to the control coefficient, the reference signal, and the output signal.

Abstract: A method couples a first bias signal to first and second internal nodes via first and second resistors, couples a second bias signal to third and fourth internal nodes via third and fourth resistors, couples the first internal node to the second internal node via a switch of a first type, and couples the third internal node to the fourth internal node via a switch of a second type. The method further couples the first internal node to the third internal node via a first transmission gate, couples the second internal node to the fourth internal node via a second transmission gate, couples a first terminal to the first and third internal nodes via first and third capacitors, respectively, and couples a second terminal to the second and fourth internal nodes via second and fourth capacitors, respectively.

Abstract: A fixed length code (FLC)-based image compression method and a device thereof. The method is utilized to compress a block containing plural pixels and includes the following steps: determining a first representative pixel, a second representative pixel and a third representative pixel from the pixels according to pixel values of the pixels, the three representative pixels being noncollinear in a color space to which the pixels correspond; generating plural first interpolated pixels by interpolation according to the first representative pixel and the third representative pixel; generating plural second interpolated pixels by interpolation according to the second representative pixel and the third representative pixel; and generating an index value for each pixel according to the three representative pixels, the first interpolated pixels and the second interpolated pixels.

Abstract: An image processing method includes: receiving a currently-input image frame and a previously-output image frame; comparing multiple first pixels corresponding to coordinates of the currently-input image frame with multiple second pixels corresponding to coordinates of the previously-output image frame, and obtaining multiple corresponding differences; obtaining multiple dynamic parameter values based on the differences and a dynamic parameter table; obtaining multiple boundary retention values based on the dynamic parameter values and a boundary operator; and obtaining multiple currently-output pixels based on the first pixels, the second pixels, and the boundary retention values. An image processing apparatus performs the image processing method, to increase accuracy of identifying a boundary adjoining a motion region and a non-motion region, and to remove an artifact of the boundary.

Abstract: A Bluetooth connection establishing method that includes the steps outlined below is provided. A new device connection period of a device to be connected is determined by a master device. The master device determines a plurality of connected devices connected to the master device. A minimum device connection period of the device connection period of the connected devices is determined. A minimum time window corresponding to the minimum device connection period is selected and anchor points of the connected devices within the minimum time window are determined. A maximum available time window is selected from the available time windows and an available time spot within the maximum available time window is selected as the new anchor point of the device to be connected.

Abstract: A data-transmission-format conversion circuit has a first data transmission interface, a second data transmission interface, and a control circuit. The control circuit is coupled to the first data transmission interface and the second data transmission interface for processing data-format conversions between the first data transmission interface and the second data transmission interface. The control circuit is further used to control the second data transmission interface to switch from a first corresponding power mode to a second corresponding power mode when the first data transmission interface is switched from a first power mode to a second power mode. The control circuit is further used to control the second data transmission interface to switch from the first corresponding power mode to a third corresponding power mode when the first data transmission interface is switched from the first power mode to a third power mode.

Abstract: A wireless transceiver device includes an operation amplification circuit, a transmitter circuit, a receiver circuit, and a transceiver control circuit. The operation amplification circuit, according to a rate parameter and a filtering parameter, filters and amplifies an input signal and outputs a processed signal. The transmitter circuit selectively uses a first ratio or second ratio as the amplification parameter, converts an input signal into an analog signal, inputs the analog signal into the operation amplification circuit, mixes the processed signal with a local oscillating frequency and then output an output signal. The receiver circuit mixes an external signal with another local oscillating frequency, inputs the mixed signal into the operation amplification circuit, and converts the processed signal into a digital signal. The transceiver control circuit selectively and electrically connects the operation amplification circuit with the transmitter circuit or the receiver circuit.

Abstract: A transceiver control circuit of a transceiver is disclosed including: a receiver circuit; a transmitter circuit; a shared filtering circuit shared by the receiver circuit and the transmitter circuit; a first mode-switch for switching signal input paths of the shared filtering circuit; a second mode-switch for switching signal output paths of the shared filtering circuit; a mode-switch control circuit for controlling the first mode-switch and the second mode-switch; a short-circuit switch coupled between two output terminals of a filter within the shared filtering circuit; and a short-circuit switch control circuit. In a period during which the transceiver transits from a receiving mode to a transmitting mode, the short-circuit switch control circuit turns on the short-circuit switch for a certain period and then turns off the short-circuit switch.

Abstract: Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.

Abstract: A circuit and method are provided for improving the accuracy of a quadrature clock. The method includes receiving a first phase, a second phase, a third phase, and a fourth phase of a first quadrature clock; outputting a first phase of a second quadrature clock in accordance with an equal sum of the first phase and the second phase of the first quadrature clock using a first summing network; outputting a second phase of the second quadrature clock in accordance with an equal sum of the second phase and the third phase of the first quadrature clock using a second summing network; outputting a third phase of the second quadrature clock in accordance with an equal sum of the third phase and the fourth phase of the first quadrature clock using a third summing network; and outputting a fourth phase of the second quadrature clock in accordance with an equal sum of the fourth phase and the first phase of the first quadrature clock using a fourth summing network.

Abstract: A wireless transceiver device includes an operation amplification circuit, a transmitter circuit, a receiver circuit, and a transceiver control circuit. The operation amplification circuit, according to a rate parameter and a filtering parameter, filters and amplifies an input signal and outputs a processed signal. The transmitter circuit selectively uses a first ratio or second ratio as the amplification parameter, converts an input signal into an analog signal, inputs the analog signal into the operation amplification circuit, mixes the processed signal with a local oscillating frequency and then output an output signal. The receiver circuit mixes an external signal with another local oscillating frequency, inputs the mixed signal into the operation amplification circuit, and converts the processed signal into a digital signal. The transceiver control circuit selectively and electrically connects the operation amplification circuit with the transmitter circuit or the receiver circuit.

Abstract: An impedance matching circuit includes a variable impedance circuit, a reference voltage generating circuit and a control circuit. The variable impedance circuit is configured for coupling to a load having an impedance and has a variable impedance; the reference voltage generating circuit coupled to the variable impedance circuit is configured to receive an input voltage of the variable impedance circuit to generate a reference voltage; and the control circuit coupled to the variable impedance circuit and configured to generate a control signal according to the reference voltage and an output voltage of the variable impedance circuit to control the variable impedance to make the variable impedance match the impedance of the load.

Abstract: A power supply device includes a power supply circuit, a detection circuit, and a control circuit. The power supply circuit is configured to output a supply voltage. The detection circuit is configured to sequentially provide a first predetermined resistance and a second predetermined resistance according to a plurality of switching signals, in order to operate with an electronic device and the supply voltage to sequentially obtain a first detection voltage and a second detection voltage. The control circuit is configured to generate the switching signals, and determine a load resistance of the electronic device according to the first detection voltage and the second detection voltage. The control circuit is further configured to determine whether the load resistance is within a predetermined resistance range, and the power supply circuit is further configured to drive the electronic device if the load resistance is within the predetermined resistance range.

Abstract: A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.