Abstract: A clock filter includes a ring oscillator comprising a plurality of inverters cascaded in a ring topology and configured to output a plurality of internal voltages including a first internal voltage and a second internal voltage. The clock filter further includes a coupling circuit configured to couple an input voltage to the first internal voltage, a sampling circuit configured to output a control voltage by sampling the second internal voltage in accordance with the input voltage, and a current source configured to output the bias current in accordance with the control voltage.

Abstract: A USB interface system capable of automatically adjusting connection speed and power consumption capability and a method thereof are provided. The method includes configuring a slave device to perform a first handshake procedure with a main device, and communicate with the main device by using a first connection specification; detecting a first power-off event by using a slave power detection module; when the first power-off event occurs, recording first power-off information by the memory unit. If the slave device is re-connected to the main device, the slave power detection module is configured to perform a second handshake process with the main device, and determine to re-communicate with the main device in a second connection specification different from the first connection specification according to the first power-off information.

Abstract: Disclosed is a circuit operating speed detecting circuit configured to detect an operating speed of a target circuit during a monitor mode. The circuit operating speed detecting circuit includes a signal generator, an adjustable delay circuit, and a signal detector. During the monitor mode, the signal generator generates a predetermined signal in a current operating condition, the adjustable delay circuit generates a delay signal according to the predetermined signal in the current operating condition, and the signal detector detects the degree of delay of the delay signal in the current operating condition so as to generate a first result if the degree of delay is not greater than a predetermined threshold and generate a second result if the degree of delay is greater than the predetermined threshold, in which the first and the second results are related to the operating speed of the target circuit.

Abstract: A clocked comparator includes a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock; a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock; a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

Abstract: A data processing system comprising a decompression circuit, configured to decompress compressed data to generate decompressed data. The decompression circuit comprises: a request transmitting terminal, configured to transmit a data receiving request indicating the decompressed data to be received; a valid information transmitting terminal, configured to transmit valid information indicating which part of the decompressed data is valid; and a data transmitting terminal, configured to transmit the decompressed data. An image processing circuit corresponds to the decompression circuit is also disclosed.

Abstract: A timing control device and a timing control method for a high frequency signal system, the timing control method respectively control trigger points of reset signals, and process the controlled reset signals and clock signals to obtain a signal group with having an absolute timing relationship.

Abstract: A comparator circuit is applied to comparing an input voltage and a reference voltage to generate a comparison result. The comparator circuit includes a resistor circuit, a current source circuit and a transistor switching circuit. The resistor circuit receives first and second input voltages in the input voltage. The current source circuit provides a first current and a second current, and the first current, the second current and the resistor circuit generate the reference voltage. The transistor switching circuit generates the comparison result at its output end according to a first control voltage and a second control voltage at its input end. The current source circuit and the resistor circuit generate the first control voltage according to the first current and the first input voltage, and generate the second control voltage according to the second current and the second input voltage.

Abstract: The present invention discloses a circuit capable of protecting low-voltage devices. The circuit includes: a pin configured to receive a signal of an external device; a control voltage generating circuit configured to generate a first control voltage according to a supply voltage to turn on a protected device when the supply voltage is at a high level, and generate a second control voltage according to a voltage of the pin to turn on the protected device when the supply voltage is at a low level; and the protected device configured to be turned on according to one of the first and the second control voltages and thereby electrically couple the pin with an internal circuit, in which the difference between the voltage of the pin and each of the first and the second control voltages is within a maximum withstanding voltage of the protected device.

Abstract: A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.

Abstract: A clocked comparator includes an upper-side sampling latch configured to output a first decision in accordance with a detection of a sign of an input voltage signal plus an offset voltage at an edge of a clock signal; a lower-side sampling latch configured to output a second decision in accordance with a detection of a sign of the input voltage signal minus the offset voltage at the edge of the clock signal; and a decision-arbitrating latch configured to receive the first decision and the second decision and output a final decision in accordance with whichever one of the first decision and the second decision that is resolved earlier.

Abstract: A circuit and method include using a first source follower of a first type to receive a first voltage from a first node and output a first current to a third node; using a second source follower of a second type to receive a second voltage from a second node and output a second current to the third node; using an AC (alternate current) coupling capacitor to couple the first node to the second node; using a feedback capacitor to couple the third node to the first node; using a shunt capacitor to shunt the third node to an AC ground; using a crystal to shunt the first node to an AC ground; providing a first bias voltage to the first node via a first DC (direct current) coupling resistor; and providing a second bias voltage to the second node via a second DC coupling resistor.

Abstract: The present invention discloses a network traffic control system capable of properly using bandwidth of a local area network (LAN). An embodiment of the system includes a master device and at least one slave device(s). The master device and the slave device(s) belong to the same LAN. The master device is configured to receive at least one flow notification packet(s) from each slave device, and determine flow allocation of the master device and each slave device according to the flow notification packet(s) and a total flow threshold. The master device is further configured to generate at least one flow control packet(s) according to the flow allocation of all the slave device(s) and transmit one or more packet(s) in accordance with the flow control packet(s) to each of the slave device(s), so that each slave device determines flow allocation of its executing network-dependent program(s) according to the one or more packet(s).

Abstract: A smart phase switching method includes setting a first phase switching threshold, a convergence upper bound, and a convergence lower bound, sampling a received signal continuously for acquiring a phase offset accumulated value of the received signal during each period, updating the first phase switching threshold to generate a second phase switching upper bound threshold and a second phase switching lower bound threshold when a plurality of phase offset accumulated values of the received signal during a first predetermined time interval fall into a range from the convergence upper bound to the convergence lower bound, and sampling the received signal continuously for determining if a phase is switched to an opposite operating point according to a phase offset accumulated value of the received signal after the second phase switching upper bound threshold and the second phase switching lower bound threshold are generated.

Abstract: A docking device includes a bus interface and a network interface controller. The bus interface is configured to be connected to a host device. The network interface controller is coupled to the bus interface and configured to receive a host-based MAC address of the host device and load the host-based MAC address for a network communication, if the host device is connected to the docking device via the bus interface. The host-based MAC address is stored in a table with a vendor specific format structure in a BIOS of the host device.

Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.

Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to a plurality of least significant bits of an input signal. The second DAC circuit is configured to output a second signal according to a plurality of most significant bits of the input signal. A first turn-on time of at least one current source circuit in the first DAC circuit is configured to set the first signal.

Abstract: The present invention discloses an image processing device and an image processing method. The image processing method includes steps of: referring to multiple frames or an auxiliary data associated with the frames to determine whether the frames contain substantially the same frames; selecting the frames according to whether the frames contain substantially the same frames to generate multiple selected frames; and performing video processing on the selected frames. When the frames do not contain substantially the same frames, the selected frames are the same as the frames, and when the frames contain substantially the same frames, the selected frames are part of the frames.

Abstract: A auxiliary Bluetooth circuit of a multi-member Bluetooth device includes: a Bluetooth communication circuit; a data transmission circuit; and a control circuit arranged to operably control the data transmission circuit to communicate data with a main Bluetooth circuit of the multi-member Bluetooth device, and arranged to utilize the Bluetooth communication circuit to sniff packets transmitted from the remote Bluetooth device during the period in which the main Bluetooth circuit conducts packet transmission with the remote Bluetooth device. When the auxiliary Bluetooth circuit missed packets transmitted from the remote Bluetooth device, the data transmission circuit is further arranged to operably receive the missed packets from the main Bluetooth circuit.

Abstract: A data management circuit with network functions and a network-based data management method are provided. The network-based data management method is employed to manage a storage device coupled to a computer that includes a processor. The method includes steps of: receiving a network packet through a network; sending the network packet to the processor or accessing the storage device, according to a network header of the network packet; and requesting the processor to access the storage device according to a remaining capacity of the storage device and/or a content of the network packet.